High-Density Memory Circuit Using Time Division Multiplexing
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Solution Overview
Problem
Modern programmable integrated circuits (ICs) face challenges in providing sufficient on-chip memory capacity for high-frequency applications, such as router processing at data rates of 400 Gigabits per second, as they typically have memory capacities in the range of 50-66 megabytes, which is insufficient for transient buffering.
Innovation Solution
A memory circuit is designed with an input stage having N input and output ports, utilizing time-division multiplexing (TDM) to consolidate multiple input ports into a single port that interfaces with a random access memory (RAM) matrix, allowing for higher data throughput and reducing the number of ports, thereby increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple input ports are used to interface with the RAM matrix, then memory bandwidth is increased, but device complexity and physical size increase
Solution Approach 1:
The patent merges N input ports into a single time-division multiplexed port that interfaces with the RAM matrix. The N:1 multiplexer consolidates multiple input streams, allowing the system to achieve high memory bandwidth equivalent to N ports while physically implementing only one port connection to the memory matrix, thereby reducing device complexity and physical size.
Solution Approach 2:
The patent implements time-division multiplexing where the single port operates in periodic time slots to serve N different input ports. Each input port is activated in sequence during its allocated time slot, creating periodic action that achieves the functional equivalent of N simultaneous ports while using only one physical port interface.
2Device complexity
If the number of ports is reduced through time-division multiplexing, then device complexity is reduced, but memory throughput may be limited
Solution Approach 1:
The single multiplexed port operates at a higher clock frequency to compensate for time-division multiplexing. By allocating time slots to N different input ports and operating at N times the required throughput rate, the system maintains high memory throughput while using only one physical port interface.
Solution Approach 2:
The patent changes the operational parameters of the single port by increasing its data rate to N times the individual port rate. This parameter change compensates for the time-division multiplexing overhead, ensuring that the aggregate throughput across all N logical ports meets the required memory bandwidth while physically using only one port.
3Productivity
If on-chip memory capacity is increased for high-frequency applications, then memory bandwidth is improved, but the physical area occupied by memory increases
Solution Approach 1:
The patent merges multiple input ports into a single time-division multiplexed port, reducing the physical infrastructure required for high-bandwidth memory access. This consolidation achieves high memory bandwidth equivalent to N ports while occupying significantly less physical area on the chip.
Solution Approach 2:
The patent transitions from a spatial dimension approach (N parallel port connections) to a temporal dimension approach (single port with time-division multiplexing). This dimensional change allows the system to achieve the same memory bandwidth through time-based separation rather than space-based parallelism, significantly reducing the physical area required for memory interfaces.
Data Source
AI summary
A memory circuit includes an input stage having N input ports and N output ports, wherein N is an integer greater than one. The memory circuit further includes an N:1 port multiplexer coupled to the N output ports of the input stage and configured to time division multiplex the N output ports to one multiplexed port. The memory circuit also includes a random access memory matrix and a 1:N port multiplexer. The memory circuit is coupled to the multiplexed port. The 1:N port multiplexer is coupled to the random access memory matrix and is configured to de-multiplex signals received from the random access memory matrix into N output ports.