Memory Circuit Testing Using Multiplexer-Configured Address Registers
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Solution Overview
Problem
Existing techniques for testing memory circuits in structured ASICs require a large number of BIST circuits, which occupy significant die area, and are not practical due to the random placement of small memory arrays during the FPGA design process.
Innovation Solution
A distributed BIST approach that uses existing circuitry to form back-to-back register pairs, allowing for high-speed testing of memory circuits without requiring extensive extra die area, by loading read and write addresses and data at the full clock signal frequency, enabling efficient testing of numerous small memory circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BIST circuits are used to test memory circuits, then testing capability is provided, but die area is significantly occupied
Solution Approach 1:
The patent makes existing address registers and data registers serve dual purposes: normal operation during design phase and BIST testing during test phase. The multiplexers enable these registers to be reconfigured for different functions, eliminating the need for dedicated BIST circuits and reducing die area while maintaining full testing capability
Solution Approach 2:
The memory circuit testing is performed using the circuit's own existing resources (address registers, data registers, multiplexers) rather than external dedicated BIST circuits. The system tests itself by reconfiguring its normal operational components for testing purposes, thereby eliminating the need for separate BIST circuitry and reducing overall die area
2Reliability
If dedicated BIST circuits are implemented for each memory array, then comprehensive testing is achieved, but device complexity increases
Solution Approach 1:
The patent creates a universal testing mechanism where the same address registers and data registers are used for both normal operation and BIST testing. The multiplexers provide a unified interface that routes signals appropriately based on whether the system is in design or test mode, simplifying the overall structure compared to having separate dedicated BIST circuits for each memory array
Solution Approach 2:
The patent merges the normal operational paths and BIST testing paths into a single integrated structure. The address registers, data registers, and multiplexers form a combined system that performs both functions, eliminating the need for separate parallel circuits and reducing overall device complexity
3Productivity
If high-speed testing at full clock frequency is implemented, then productivity is improved, but timing requirements become more stringent
Solution Approach 1:
The patent dynamically reconfigures the circuit timing by using clock enable signals and mode control to switch between design mode and BIST test mode. During BIST testing, the system operates at full clock frequency with synchronized timing controlled by the mode signal, allowing high-speed testing while maintaining proper timing relationships through dynamic control of the existing clocking infrastructure
Data Source
AI summary
An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.