Multi-port Memory Circuit Timing Control for Interference Reduction
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Solution Overview
Problem
Existing memory circuits face challenges in efficiently managing data access and power consumption due to interference between simultaneous memory accesses, leading to issues like 'read disturb' and high peak power demand.
Innovation Solution
A memory circuit with a timing controller that introduces a time delay between first and second access modes, allowing for flexible operation by controlling the timing of access ports to reduce interference and optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous memory accesses are performed through multiple access ports, then data throughput is increased, but interference between accesses occurs leading to read disturb and high peak power consumption
Solution Approach 1:
The patent implements dynamic timing control by making the time delay between first and second access operations adjustable based on operational mode. In performance mode, a first time delay is applied, while in power-saving mode, a second (different) time delay is applied. This dynamic adjustment allows the system to optimize between throughput and interference reduction depending on current operational requirements.
Solution Approach 2:
The patent changes the timing parameter (time delay between accesses) to resolve the contradiction. By modifying this temporal parameter, the system can achieve different operational characteristics: shorter delays for higher throughput or longer delays for reduced interference and power consumption. This parameter adjustment enables the system to adapt to different operational modes without hardware changes.
2Object-affected harmful factors
If time delay between first and second access modes is increased, then interference and peak power consumption are reduced, but data output speed decreases
Solution Approach 1:
The system dynamically adjusts the time delay parameter based on the selected operational mode. When performance is prioritized, a shorter time delay is used to maintain high data output speed. When power consumption is prioritized, a longer time delay is applied to reduce peak power consumption. This dynamic control resolves the contradiction by allowing the system to adapt to different operational priorities.
Solution Approach 2:
The patent employs periodic access patterns with controlled timing intervals between first and second access modes. By structuring accesses with specific time delays, the system can manage power consumption peaks while maintaining acceptable throughput. The periodic nature of memory accesses allows for predictable timing control to balance speed and power efficiency.
3Adaptability or versatility
If flexible access mode selection is provided, then system performance optimization is enabled, but device complexity increases
Solution Approach 1:
The timing controller is designed to perform multiple functions: it controls the time delay between accesses, responds to mode selection signals, and adapts timing parameters based on operational requirements. This multi-functionality reduces the need for separate dedicated circuits for different control tasks, thereby managing complexity while providing flexible access mode selection and performance optimization capabilities.
Data Source
AI summary
A memory circuit includes first and second word lines, a plurality of memory cells and a timing controller. Each memory cell includes a first access port and a second access port. The first access port is coupled to the first word line and configured to be enabled by a first word line signal on the first word line. The second access port is coupled to the second word line and configured to be enabled by a second word line signal on the second word line. The timing controller is configured to receive a timing select signal and to control a time delay between the first word line signal and the second word line signal to be different in response to different first and second states of the timing select signal.