Memory Circuit With Controlled Transistor Gate Potential
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Solution Overview
Problem
Conventional memory circuits face high power consumption due to leakage current and require continuous power supply to retain data, making them inefficient in terms of energy usage.
Innovation Solution
A memory circuit design utilizing inverters composed of field-effect transistors with the same conductivity type, where the gate potential of at least one transistor is controlled by a control signal to minimize leakage current and allow data retention even without continuous power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory circuits use inverters with depletion transistors to maintain data, then data storage function is achieved, but leakage current flows continuously increasing power consumption
Solution Approach 1:
The patent applies dynamics by making the transistor states changeable between active and inactive modes. The memory circuit transitions from a static state where current always flows to a dynamic state where current flow is controlled - during write operations transistors are active, during read operations specific transistors are activated, and during hold periods transistors are deactivated to minimize leakage. This dynamic control resolves the contradiction between maintaining data storage reliability and reducing continuous power consumption.
Solution Approach 2:
The patent changes the electrical parameters of the transistors by applying different gate potentials. By controlling the gate voltage of the sixth and seventh transistors, the circuit can switch between different operational states - when gate potential is applied, the transistors conduct; when gate potential is removed or reduced, the transistors enter high-impedance state with minimal leakage current. This parameter control allows the system to maintain data while minimizing energy loss during hold periods.
2Reliability
If power supply voltage is continuously supplied to retain data in conventional memory circuits, then data is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by supplying power supply voltage and control signals only when needed - during write operations and read operations. During hold periods, the power supply can be disconnected or voltage reduced, and the memory circuit maintains data through the stable state of the cross-coupled inverters and controlled transistor states. This periodic power supply approach eliminates continuous power consumption while maintaining data retention reliability.
Solution Approach 2:
The memory circuit exhibits self-service characteristics where the cross-coupled inverter structure inherently maintains the stored data state without requiring continuous external control signals or power. Once data is written into the stable state of the inverters, the circuit maintains this state through its own internal feedback mechanism, requiring minimal external intervention and power during hold periods.
3Quantity of substance
If memory circuit capacity is increased to store more data, then storage capability is improved, but power consumption increases due to leakage current
Solution Approach 1:
The patent applies segmentation by dividing the memory circuit into independently controllable units - each memory cell with its own set of transistors and inverters can be controlled separately. This allows the system to activate only the specific memory cells needed for current operations while keeping others in a low-power state, thus increasing total storage capacity without proportionally increasing overall power consumption from leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption by minimizing leakage current and enables data retention in a nonvolatile manner, even when the power supply is stopped, thus enhancing energy efficiency.
Implementation Method 1
a gate of the first field-effect transistor serves as an input terminal of the inverter. The first field-effect transistor controls whether a potential of an output terminal of the inverter is set at a first potential or not in accordance with a potential of the input terminal of the inverter
Data Source
AI summary
To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.