Memory Circuit Direct Transistor-Level Signal Access
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Solution Overview
Problem
Conventional memory access circuits in integrated circuits suffer from high interconnection resistance and RC delay, leading to increased access latency, power consumption, and circuit area, which adversely affect data access efficiency.
Innovation Solution
The implementation of a memory circuit with a memory cell array and an I/O connection interface configured to receive transistor-level operation signals directly from an external memory controller, allowing for direct transmission and reception of transistor-level data signals through bumpless interconnectors, eliminating the need for additional buffering or driving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional input/output interfaces and memory control circuits are used for communication between memory and system dies, then data access efficiency deteriorates due to high interconnection resistance and RC delay, but using these conventional interfaces ensures compatibility and standardized communication protocols
Solution Approach 1:
The patent extracts and removes the conventional input/output interfaces and memory control circuits from the memory die, eliminating the sources of high interconnection resistance and RC delay. The memory die is designed to directly interface with the system die through simplified connection structures, taking out the problematic conventional interfaces that were causing access efficiency deterioration.
Solution Approach 2:
The patent merges the memory control functionality directly into the system die, combining what were previously separate functions. This integration allows the system die to directly control memory operations without requiring separate control circuits on the memory die, reducing the number of interconnections and eliminating RC delay issues associated with conventional interfaces.
2Reliability
If additional buffering or driving circuits are added to overcome interconnection resistance, then power consumption and circuit area increase, but without such circuits data access efficiency remains poor
Solution Approach 1:
The patent implements self-service by designing the memory circuit to inherently tolerate and operate with the existing interconnection characteristics without requiring external buffering or driving circuits. The memory cell array and I/O connection interface are designed to directly handle signal transmission across the interconnectors, with the circuit itself adapting to the transmission medium rather than adding complex compensation circuits.
Solution Approach 2:
The patent changes the operating parameters of the memory circuit by using transistor-level operation signals that are optimized for direct transmission through the bumpless interconnectors. The I/O connection interface is designed to operate at parameters that match the interconnection characteristics, eliminating the need for additional buffering circuits while maintaining signal integrity.
3Loss of time
If bumpless interconnectors are used for direct transmission, then access latency and circuit area are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection system into distinct functional regions: the bumpless interconnector region for high-speed signal transmission and the bonding interface region for mechanical alignment. This segmentation allows each region to be optimized independently, with the bumpless interconnectors designed for minimal RC delay and the bonding interfaces designed with alignment tolerance features.
Solution Approach 2:
The patent introduces the I/O connection interface as an intermediary structure that mediates between the bumpless interconnectors and the external environment. This intermediary provides signal conditioning and level shifting while maintaining the benefits of direct bumpless interconnection, allowing the system to achieve low access latency without requiring extreme manufacturing precision throughout the entire signal path.
Data Source
AI summary
System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.