Memory Circuit Voltage Domain Segmentation for Write Reliability

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Solution Overview

Problem

Memory circuits face challenges in efficiently managing multiple power domains, leading to performance limitations and increased power consumption due to the need for separate voltage levels for memory arrays and other circuits.

Innovation Solution

A memory circuit design that includes a bit line, a power node with a memory domain power voltage level, a reference node, and pass gates and drivers that selectively couple the bit line to these nodes based on distinct power voltage levels, allowing for reliable operation and reduced power usage by avoiding the need for dummy read operations and minimizing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory circuits use a higher power voltage level to support reliable memory cell functioning, then memory reliability is improved, but overall circuit power consumption increases

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidcircuit power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The circuit is divided into multiple power domains: a first power domain with a higher voltage level for the memory array and a second power domain with a lower voltage level for other circuits. This segmentation allows each domain to operate at its optimal voltage level, ensuring memory reliability while reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different parts of the circuit are assigned different voltage levels according to their specific requirements. The memory array operates at a higher voltage for reliable functioning, while other circuits operate at a lower voltage to reduce power consumption. This local quality approach optimizes both reliability and energy efficiency.

Inventive Principle:
Principle #3Local quality

2Use of energy by stationary object

If separate voltage levels are used for memory arrays and other circuits, then power efficiency is improved, but circuit complexity increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

Pass gates are introduced as intermediary components to selectively couple bit lines to either the first power domain or the second power domain based on control signals. These pass gates manage the complexity of multiple voltage levels by providing controlled access to different power domains without requiring complex voltage conversion circuits throughout the entire system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If pass gates selectively couple bit lines to power nodes based on control signals, then write reliability is improved, but additional circuit components are required

Engineering Contradiction:
Improvewrite operation reliabilityVSAvoidcircuit components
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Pass gates are activated in advance of the write operation to pre-establish the correct coupling between bit lines and power nodes. By preliminarily configuring the circuit state before the actual write operation, the system ensures that voltage transitions occur reliably without requiring additional corrective components or operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11776622B2Circuit and method of writing to a bit cell
Publication Date: 2023.10.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11776622B2 patent drawing
  • US11776622B2 patent drawing
  • US11776622B2 patent drawing

AI summary

A circuit includes first and second bit lines, a second power node having a voltage level below that of a first power node, a reference node having a reference voltage level, first and second pass gates and drivers, first and second logic gates coupled to the second power node, first and second conversion circuits coupled between the first power node and respective first and second logic and pass gates, and first and second NOR gates coupled between the second power node and respective first and second logic gates and drivers. The first and second pass gates selectively couple the first and second bit lines to the first power node responsive to the respective second and first logic gates and conversion circuits, and the first and second drivers selectively couple the first and second bit lines to the reference node responsive to the respective first and second logic and NOR gates.