Memory Circuit Configuration for Weak Cell Compensation
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Solution Overview
Problem
Memory circuits face reduced operating speeds and increased power consumption due to low operating voltages, which are exacerbated by variations in memory cell physical properties and manufacturing processes, leading to slower read operation speeds.
Innovation Solution
A memory circuit configuration that identifies weak cells through test read operations and pairs them with redundant rows, enabling simultaneous read and write operations across both rows to enhance overall operating speed and allow lower voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If memory circuits are operated at low voltages to limit power consumption, then power consumption is reduced, but circuit speeds and memory access speeds decrease
Solution Approach 1:
The patent performs preliminary characterization of memory cells during manufacturing to identify weak cells before the memory device is put into service. This advance knowledge allows the system to compensate for slow cell performance without increasing operating voltage, thereby maintaining low power consumption while achieving acceptable access speeds through alternative access patterns and timing adjustments.
Solution Approach 2:
The patent changes operational parameters such as access timing, row activation sequences, and data read/write scheduling based on the identified weak cells. By adjusting these parameters rather than increasing voltage, the system maintains low power consumption while optimizing access speeds for cells with varying performance characteristics.
2Use of energy by stationary object
If memory circuits are operated at low voltages, then power consumption is reduced, but manufacturing process variations lead to slower read operation speeds
Solution Approach 1:
The patent performs preliminary characterization of memory cells during manufacturing to identify weak cells before the memory device is put into service. This advance knowledge allows the system to compensate for slow cell performance without increasing operating voltage, thereby maintaining low power consumption while achieving acceptable access speeds through alternative access patterns and timing adjustments.
Solution Approach 2:
The patent uses feedback from the preliminary cell characterization data to adjust access patterns, timing parameters, and row activation strategies. This feedback mechanism allows the system to adapt to manufacturing variations in each specific device, maintaining consistent performance across different manufacturing batches while operating at low voltages.
3Speed
If weak cells are identified and compensated through redundant rows, then read operation speed is improved, but device complexity increases
Solution Approach 1:
The patent creates simplified copies or representations of weak cell locations during manufacturing characterization. Instead of implementing full redundant rows for all cells, the system uses compact data structures to represent weak cell positions and applies targeted access patterns only where needed, reducing the complexity overhead while still improving read speeds for affected cells.
Data Source
AI summary
A circuit includes a memory array, a control circuit configured to identify an address of a first row containing a weak cell, and store corresponding address information in a storage device, and an address decoding circuit including NAND pairs, inverter pairs, and a logic tree. Each NAND pair receives corresponding bits of the address information and the address of the first row and corresponding inverted bits of the address information and the address of the first row inverted by corresponding inverter pairs, and output terminals of the NAND pairs are connected to the logic tree. The logic tree matches the address information with the address of the first row based on output logic levels from the NAND pairs and, in response to the corresponding address information matching the address of the first row, activates a second row of the memory array simultaneously with the first row being activated.