Memory Circuit Word Line Control Reducing Rushing Power
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Solution Overview
Problem
Conventional memory circuits face performance degradation due to high 'rushing power' and long 'wakeup time' when switching from power down mode to active mode, as they require significant power to recharge circuit components.
Innovation Solution
The memory circuit design incorporates specific configurations of PMOS and NMOS transistors and a control circuit to manage gate voltages, reducing leakage current and enabling faster mode transitions by optimizing transistor states during power down and active modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply to the memory array is cut off in power down mode, then the power consumption is further reduced, but the rushing power and wakeup time increase when switching to active mode
Solution Approach 1:
The power supply control is segmented into multiple PMOS transistors (first PMOS transistor and second PMOS transistor) that can be independently controlled. This allows the power supply to be restored in stages rather than all at once, reducing the rushing power when switching from power down mode to active mode.
Solution Approach 2:
The first PMOS transistor is turned on before the second PMOS transistor when exiting power down mode, preliminarily establishing a partial power supply path. This preliminary action reduces the sudden power demand by gradually restoring power to the memory array.
2Loss of energy
If the power supply to the memory array is cut off in power down mode, then the power consumption is further reduced, but the wakeup time increases when switching to active mode
Solution Approach 1:
The power restoration process is segmented into two stages controlled by separate PMOS transistors. This segmentation allows for optimized timing control, where the first PMOS transistor activates earlier to begin charging, thereby reducing the total wakeup time while still maintaining low power consumption during power down mode.
Solution Approach 2:
The power supply control uses dynamic switching of the first and second PMOS transistors based on the operational mode. The control signals dynamically adjust the conductivity of these transistors to optimize both power consumption and wakeup time, making the system adaptable to different operational states.
3Power
If delay elements are used to sequentially turn on PMOS transistors to reduce rushing power, then the rushing power is reduced, but the wakeup time period is extended
Solution Approach 1:
The invention changes the parameters of the PMOS transistors, specifically making the area of the first PMOS transistor larger than the area of the second PMOS transistor. This parameter change allows the first PMOS transistor to handle higher current during the initial power restoration phase, reducing rushing power without requiring sequential delay elements, thus avoiding extension of wakeup time.
Data Source
AI summary
A word line control circuit includes a first PMOS transistor having a gate coupled to a first selection signal; a first NMOS transistor, coupled between a second node and a second voltage terminal, having a gate coupled to an inverted first selection signal, wherein the inverted first selection signal is obtained by inverting the first selection signal; and a plurality of word line drivers, at least one of the word line drivers comprising a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first voltage terminal, a negative power terminal of the first inverter is coupled to the second node, a positive power terminal of the second inverter is coupled to the first node, and a negative power terminal of the second inverter is coupled to the second voltage terminal.