Memory Clamping Circuit Reduces Rock Bottom Leakage
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Solution Overview
Problem
Current memory systems face challenges in reducing rock bottom sleep current (RBSC), a significant contributor to idle power consumption in mobile devices, particularly due to gate leakage and subthreshold leakage currents during sleep modes.
Innovation Solution
The implementation of a memory system with a word line (WL) driver circuit and a clamping circuit that includes transistors and head switches to selectively couple the WL to a reference potential node and a voltage rail, respectively, allowing the control signal to float when the head switch is open, thereby reducing gate leakage and subthreshold leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control signal is kept at a fixed voltage level during sleep mode, then the transistor gate maintains a defined state, but gate leakage current and subthreshold leakage current increase
Solution Approach 1:
The patent extracts the voltage supply connection from the control signal node during sleep mode by opening the first head switch, completely disconnecting the voltage rail from the logic supply input. This extraction eliminates the leakage current path while the second head switch maintains necessary connections for memory cell retention.
Solution Approach 2:
The patent dynamically changes the connection state of control signal nodes during sleep mode. The first head switch opens to float the control signal, while the second head switch closes to connect memory cell word lines to reference potential. This dynamic reconfiguration reduces leakage while maintaining functional requirements.
2Loss of energy
If the control signal is left floating to reduce leakage current, then gate leakage and subthreshold leakage are minimized, but the transistor gate may accumulate charge or become unstable
Solution Approach 1:
The patent segments the head switch control into two independent switches: the first head switch controls the voltage supply connection to logic, and the second head switch controls the memory cell word line connection. This segmentation allows independent optimization of leakage reduction and signal stability for different circuit portions.
Solution Approach 2:
The second head switch acts as an intermediary that maintains the reference potential connection to memory cell word lines during sleep mode, ensuring stable voltage levels at critical nodes even while the control signal logic is floated to reduce leakage.
3Loss of energy
If additional head switches and clamping circuits are added to reduce leakage, then RBSC is minimized, but circuit complexity increases
Solution Approach 1:
The head switches serve multiple functions: they control voltage supply to logic, manage memory cell word line connections, and enable sleep mode operation. This multi-functionality reduces the need for separate dedicated leakage reduction circuits, optimizing the complexity-benefit ratio.
Solution Approach 2:
The patent combines the sleep mode control functionality with the existing head switch structure used for memory cell control. By merging these functions into a unified switch control mechanism, the patent reduces overall circuit complexity while achieving leakage reduction goals.
Data Source
AI summary
Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.