Memory Clock Generation for Built-In Self-Test Speed
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Solution Overview
Problem
Integrated circuits with embedded RAM face challenges in testing due to the RAM's size and accessibility, leading to increased gate delays and reduced operation speed when using built-in self-test circuits, which complicates chip manufacturing and testing efficiency.
Innovation Solution
A memory device with a built-in clock generation circuit that directly receives clock signals through input/output pins, reducing gate delays by selecting between clock signals for normal operation and self-test modes, thereby enhancing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a built-in self-test circuit is added to the memory device, then the testing capability is improved, but the gate delay increases and operation speed decreases
Solution Approach 1:
The clock generation circuit is segmented into multiple independent clock generation units, each capable of generating clock signals for specific functions. This allows the self-test function to operate with dedicated clock signals without interfering with the timing-critical normal operation paths, thereby maintaining high operation speed while enabling comprehensive testing capability.
Solution Approach 2:
A clock selection unit acts as an intermediary between the clock generation units and the functional circuits. This intermediary selectively routes appropriate clock signals to different circuits based on operational mode, ensuring that self-test operations receive necessary clock signals without introducing delays to the normal operation paths, thus resolving the conflict between testing capability and operation speed.
2Quantity of substance
If the embedded RAM occupies a significant portion of the chip area, then the memory capacity is improved, but the probability of defects increases and testing difficulty increases
Solution Approach 1:
The embedded RAM is divided into multiple banks or segments, each with dedicated test access paths. This segmentation allows independent testing of smaller memory sections, reducing the overall defect probability by isolating potential failures and enabling more effective defect detection and localization in large-capacity memory structures.
Solution Approach 2:
The clock generation circuit is designed with multi-functionality to serve both normal memory operations and self-test operations. By providing universal clock signal generation and selection capabilities, the circuit enables comprehensive testing of the large embedded RAM without requiring additional external test equipment, thus managing the increased defect probability inherent in large memory capacities.
3Quantity of substance
If the embedded RAM is made larger, then the memory capacity is improved, but the testability of other functions on chip is impaired
Solution Approach 1:
The clock generation system is segmented into multiple independent units that can be selectively activated. This allows test patterns to be applied to specific memory banks or functional blocks without requiring the entire system to be in test mode, thereby maintaining testability of other chip functions even when embedded RAM capacity is large.
Solution Approach 2:
The clock selection unit dynamically switches between different clock sources based on the operational mode and the specific function being tested. This dynamic clock management enables flexible test configurations where large embedded RAM can be tested while other functions continue to operate with their own dedicated clock signals, preserving overall chip testability.
Data Source
AI summary
A circuit includes one or more functional circuits, and a clock generation circuit operatively coupled to the one or more functional circuits. The clock generation circuit is configured to: receive a control signal to switch the one or more functional circuits between a first operation mode and a second operation mode; receive a first clock signal and a second clock signal corresponding to the first operation mode and the second operation mode, respectively; and output, to the one or more functional circuits, a clock pulse signal based on either the first clock signal or the second clock signal. The clock generation circuit is configured to generate either a first conduction path to output the clock pulse signal or a second conduction path to output the clock pulse signal. Each of the first and second conduction paths includes a predefined number of gate delays.