Semiconductor Memory Clock Buffer DLL Power Optimization
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Solution Overview
Problem
Existing semiconductor memory apparatuses face challenges in reducing power consumption when operating at high speeds, particularly in synchronizing data transmission with clock signals, as current delay-locked loop (DLL) circuits are inefficient in managing power usage.
Innovation Solution
The semiconductor memory apparatus incorporates a clock buffer, delay-locked loop block, operation control block, and phase comparison units to generate and synchronize internal and feedback clock signals, allowing for dynamic adjustment of delay times and activation control signals to match phases, thereby reducing power consumption by deactivating the delay-locked loop during phase synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a delay-locked loop (DLL) circuit is used to synchronize data transmission with clock signals at high speed, then the semiconductor memory apparatus can operate in synchronization with the clock signal, but the power consumption increases
Solution Approach 1:
The DLL circuit's operation is made dynamic through the activation control signal. The circuit transitions between active and inactive states based on whether phase comparison is needed, allowing the system to maintain synchronization capability when required while conserving power when the DLL is not actively adjusting delays
Solution Approach 2:
The activation control signal enables periodic operation of the DLL circuit rather than continuous operation. The circuit is activated only during periods when phase comparison indicates synchronization is needed, and deactivated during periods when synchronization is maintained, creating a periodic on/off pattern that reduces average power consumption
2Reliability
If continuous phase comparison and delay adjustments are performed in the DLL circuit, then clock signal synchronization is maintained, but power consumption increases
Solution Approach 1:
The activation control signal provides feedback control for the DLL circuit. The phase comparison unit monitors the synchronization status and generates the activation control signal based on whether phase alignment is achieved. This feedback mechanism allows the system to stop adjustments once synchronization is reached, eliminating the need for continuous power-consuming adjustments
Solution Approach 2:
The DLL circuit becomes self-regulating through the activation control mechanism. Once the phase comparison indicates that synchronization is achieved, the activation control signal automatically deactivates the DLL circuit, allowing it to maintain its locked state without continuous external control or power input
Data Source
AI summary
A semiconductor memory apparatus may include a clock buffer configured to receive an external clock signal, buffer the external clock signal in response to an activation control signal, and the clock buffer configured to output an internal clock signal in response to an activation control signal. The semiconductor memory apparatus may also include a delay-locked loop block configured to receive the internal clock signal outputted from the clock buffer and compare phases of the internal clock signal and a feedback clock signal, and responsively generate a delay-locked clock signal. The semiconductor memory apparatus may also include an operation control block configured to responsively generate the activation control signal which is received by the clock buffer in accordance with a result of comparing the phases of the internal clock signal and the feedback clock signal, in response to receiving a read signal.