Self-Reset Memory Clock Buffer With Feedback and Tri-State Keeper
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Solution Overview
Problem
Conventional clock buffers in memory devices face issues such as reliance on hard delays leading to timing violations, increased circuit area due to multiple transistors, high load on external clock signals, and failure at lower supply voltages due to contention between clock generator and keeper circuit.
Innovation Solution
A cross-coupled logic circuit with a feedback loop is used, enabling self-reset functionality, reducing the need for hard delays, eliminating one nFET transistor, and replacing the latch with a tri-state inverter to maintain signal integrity at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hard delay circuit is used to ensure proper clock timing, then the clock buffer can generate the internal memory clock, but timing violations occur and the hold time must be extended
Solution Approach 1:
The patent applies feedback by monitoring the output clock signal and using it to control the pull-down transistor. The output clock signal feeds back to the gate of the pull-down transistor, automatically disabling it when the clock transitions to high state, thereby eliminating the need for hard delay circuits and extended hold times
Solution Approach 2:
The clock buffer circuit performs self-service by using its own output clock signal to control its internal pull-down transistor. The circuit automatically regulates its own operation without requiring external delay circuits or extended hold time constraints, achieving self-timed operation
2Ease of operation
If two nFET transistors are used in the pull-down circuit to combine clock signals, then the logic function is achieved, but the circuit area increases and storage density decreases
Solution Approach 1:
The patent extracts and removes one of the two nFET transistors from the conventional pull-down circuit. By using the feedback mechanism from the output clock signal, the circuit achieves the same logic function with only one nFET transistor, thereby reducing circuit area and improving storage density
Solution Approach 2:
The patent changes the operational parameters of the remaining nFET transistor by controlling it with the feedback clock signal instead of using a dedicated delay signal. This parameter change allows the single transistor to perform the logic function previously requiring two transistors
3Ease of operation
If two nFET transistors are used in the pull-down circuit, then the logic function is achieved, but the capacitance increases the load on the external clock
Solution Approach 1:
The patent extracts and removes one nFET transistor from the pull-down circuit, directly reducing the total capacitance that loads the external clock signal. The feedback mechanism ensures the remaining transistor is properly controlled without requiring additional capacitance
4Duration of action of stationary object
If a latch is used in the keeper circuit, then the clock signal is maintained, but contention occurs between the clock generator and keeper circuit at lower supply voltages
Solution Approach 1:
The patent applies feedback control to the keeper circuit, using the output clock signal to automatically control the keeper transistor. This feedback mechanism eliminates contention between the clock generator and keeper circuit by ensuring the keeper is only active when needed, enabling reliable operation at lower supply voltages
Solution Approach 2:
The patent makes the keeper circuit dynamic by controlling it with the feedback clock signal rather than using a static latch. The keeper transistor is dynamically enabled and disabled based on the clock signal state, allowing the circuit to adapt to lower supply voltage conditions without contention
5Adaptability or versatility
If the delay is set longer than the minimum time required, then timing violations are avoided under varying PVT conditions, but the hold time increases and affects setup time for memory latches
Solution Approach 1:
The patent uses feedback from the actual output clock signal to control the pull-down transistor, replacing the fixed delay circuit. This feedback mechanism automatically adapts to PVT variations without requiring a fixed, conservative delay time, thereby minimizing hold time while maintaining timing reliability across all operating conditions
Data Source
AI summary
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.