Memory Clock Buffer Power Management via Selective PLL Coupling
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Solution Overview
Problem
Current DDR memory topologies face challenges in managing additive jitter, clock skew, and margin constraints at high transfer rates, leading to increased power consumption and reduced battery life in portable systems and increased thermal loads in enterprise systems.
Innovation Solution
A clock buffer device for memory modules is introduced, featuring a phase-locked loop (PLL) configuration that allows for selective coupling of PLL outputs to clock output buffers, enabling power reduction by disabling PLLs during lower transfer rates and utilizing single-PLL or dual-PLL modes at higher rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual PLL configuration is used to provide both first and second clock signals, then clock signal availability is improved, but power consumption increases
Solution Approach 1:
The system dynamically configures PLL operation modes based on system requirements. The clock buffer device can operate in dual-PLL mode when both first and second clock signals are needed, and switch to single-PLL mode when only one clock signal is required, thereby adapting power consumption to actual operational needs
Solution Approach 2:
The invention changes the operational parameters of the PLL by providing different clock input signals (first clock signal and second clock signal) and selectively enabling different PLL instances based on system configuration. This allows the system to optimize between power consumption and clock signal availability by adjusting which PLL is active
2Speed
If clock buffer device operates at high transfer rates, then data transfer speed is improved, but power consumption and thermal load increase
Solution Approach 1:
The clock buffer device is segmented into multiple independent PLL instances (first PLL and second PLL), each capable of operating independently. This segmentation allows the system to activate only the necessary PLL for the current transfer rate requirement, reducing overall power consumption while maintaining high transfer rate capability when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves significant power savings, with up to 40 mW reduction in power draw during bypass mode and optimized power management across different transfer rates and system architectures, thereby extending battery life and reducing thermal loads.
Implementation Method 1
a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL
Data Source
AI summary
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.