Memory Device Clock Buffer Frequency Band Switching
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Solution Overview
Problem
The increasing power consumption in electronic devices due to high-integration, high-performance memory systems, particularly because of the high frequency of clock signals, which leads to higher power consumption in memory devices like SDRAM.
Innovation Solution
A memory device with first and second data buffer sets and clock buffers that adjust clock signal distribution based on frequency bands, allowing the clock buffers to operate as single or differential input buffers depending on the frequency band, optimizing clock signal quality and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is increased to achieve high-performance memory operations, then the processing speed and data throughput are improved, but the power consumption of the memory device increases proportionally
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by providing multiple clock signal frequencies (first frequency band and second frequency band) and selectively switching between them based on operating conditions. The clock buffer dynamically changes the clock frequency provided to data buffer sets according to whether high-performance or power-saving mode is required, resolving the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal from a fixed value to a variable that can switch between at least two distinct frequency bands. By adjusting the clock frequency parameter dynamically, the system achieves high processing speed when needed while reducing power consumption during normal operations, thus resolving the technical contradiction.
2Productivity
If multiple data buffer sets operate simultaneously at high frequency to increase data throughput, then the productivity is improved, but the overall power consumption increases due to all buffers consuming power during each clock transition
Solution Approach 1:
The patent enables dynamic control of clock frequency for multiple data buffer sets. By switching between first and second frequency bands, the system can optimize the balance between total data throughput and cumulative power consumption across all buffer sets, allowing high productivity only when absolutely necessary while reducing energy loss during normal operation.
Data Source
AI summary
A memory device includes a first data buffer receiving data of a first frequency band or a second frequency band, a first clock buffer providing a clock signal of the first frequency band to the first data buffer when the first data buffer receives the data of the first frequency band and providing a clock signal of the second frequency band to the first data buffer when the first data buffer receives the data of the second frequency band, a second data buffer receiving the data of the first frequency band or the second frequency band and receiving the clock signal of the second frequency band from the first clock buffer in response to receiving the data of the second frequency band, and a second clock buffer providing the clock signal of the first frequency band to the second data buffer in a first frequency band operation.