Memory Controller Clock Calibration During Voltage Ramps
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Solution Overview
Problem
Existing memory subsystems face challenges in efficiently performing calibrations during performance state changes, particularly when large voltage increments occur, leading to disruptions in memory traffic and inadequate timing adjustments of clock signals.
Innovation Solution
A memory controller performs background calibrations using a ring oscillator on the memory side to generate count values, adjusting the delay of clock signals based on these values during voltage ramps, allowing normal memory transactions to continue during the transition to a new performance state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If calibrations are performed during performance state changes using traditional methods, then timing accuracy is improved, but memory traffic is disrupted and system productivity decreases
Solution Approach 1:
The patent performs calibrations preliminarily during performance state changes before normal memory operations resume. The memory controller executes calibration routines that adjust timing parameters in advance, ensuring timing accuracy is established before memory traffic needs to flow, thus resolving the contradiction between achieving precise timing and maintaining productivity
Solution Approach 2:
The patent implements optimized calibration sequences that rush through essential calibration steps during performance state transitions. By skipping non-critical calibration operations or performing them in compressed time windows, the system achieves sufficient timing accuracy while minimizing the duration of memory traffic disruption, thereby maintaining higher overall productivity
2Speed
If large voltage increments are used during performance state changes, then transition speed is improved, but timing margins become inadequate and calibration becomes more difficult
Solution Approach 1:
The patent employs dynamic voltage transition strategies where the voltage increment size is adjusted based on real-time feedback from timing margin measurements. During performance state changes, the system initially uses larger voltage increments for fast transitions, then dynamically reduces increment size near the target voltage to fine-tune timing margins, thus achieving both fast transition speed and precise timing accuracy
Solution Approach 2:
The patent implements feedback mechanisms that monitor timing margins during voltage transitions and adjust subsequent voltage increment steps accordingly. When timing margins fall below thresholds, the system reduces voltage increment size or pauses transitions to allow calibration, ensuring that large voltage increments do not compromise timing precision while maintaining overall transition efficiency
3Measurement precision
If multiple calibrations are performed sequentially during performance state changes, then timing precision is improved, but calibration time increases and system responsiveness decreases
Solution Approach 1:
The patent segments the calibration process into multiple independent calibration routines that can be executed in parallel or overlapping time windows. Instead of performing all calibrations sequentially, the system divides timing, voltage, and other parameter calibrations into separate modules that operate concurrently during performance state changes, reducing total calibration time while maintaining precision through comprehensive coverage
Solution Approach 2:
The patent maintains continuity of calibration actions by overlapping calibration routines with non-critical memory operations or by performing calibrations in background threads that do not block main processing. This allows timing precision to be improved through multiple calibrations while minimizing the perceived calibration duration to the system, as useful actions continue uninterrupted or with minimal interruption
Data Source
AI summary
An apparatus for performing memory calibrations during a performance state change is disclosed. A memory controller is configured to convey a clock signal to a memory and includes a calibration control circuit configured to perform a plurality of calibrations of the clock signal during a change from a first one to a second one of a plurality of performance states, and a delay circuit configured to apply a delay to clock signal conveyed to the memory. In performing a one of the calibrations, the calibration control circuit is configured to convey, to the memory, a first command to begin a timing test that generates a count value indicative of a current voltage of the memory, receive the count value from the memory at a conclusion of the timing test, and cause the delay circuit to adjust, based on the count value, the delay applied to the clock signal.