Memory Clock Distribution Using CML to Reduce Jitter
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Solution Overview
Problem
Conventional semiconductor memory devices experience increased jitter components in clock signals due to poor noise rejection characteristics of CMOS circuits, leading to reduced stability at high speeds.
Innovation Solution
Implementing a Current Mode Logic (CML) circuit for clock distribution, which includes repeaters operating at a CML level, and a DCC circuit that corrects duty cycles using feedback from the clock transfer portion, along with arranging the clock supply portion closer to EDC output portions to minimize noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS circuits are used for clock distribution, then the device complexity is reduced and ease of manufacture is improved, but noise rejection characteristics deteriorate leading to increased jitter components
Solution Approach 1:
The patent changes the operating level parameter from CMOS level to CML (Current Mode Logic) level for the clock distribution circuit. This parameter change transforms the circuit's noise rejection characteristics while maintaining manufacturability through standard semiconductor fabrication processes.
2Ease of manufacture
If CMOS circuits are used for clock distribution, then manufacturing simplicity is maintained, but jitter components increase reducing clock signal stability
Solution Approach 1:
The patent applies CML level operation to the clock distribution circuit, changing the voltage swing and current operation parameters. This results in reduced jitter components and improved clock signal stability while remaining compatible with standard semiconductor manufacturing.
3Adaptability or versatility
If clock supply portion is placed farther from data output portions, then layout flexibility is improved, but noise and jitter increase affecting clock characteristics
Solution Approach 1:
The patent applies different design considerations to different regions: the clock supply portion is strategically positioned close to noise-sensitive data output portions, while other areas maintain layout flexibility. This local optimization ensures good clock characteristics where needed without compromising overall design adaptability.
Data Source
AI summary
A semiconductor memory device includes a clock supply portion for providing an external clock to the interior of the memory device, a clock transfer portion for transferring the clock from the clock supply portion to each of elements in the memory device and data output portions for outputting data in synchronism the clock from the clock transfer portion, wherein the clock from the clock supply portion to the clock transfer portion swings at a current mode logic (CML) level.