Memory Clock Delay Switching for Read-Write PPA Balance
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Solution Overview
Problem
Current memory circuit designs provide constant clock latency, independent of read or write operations, leading to sub-optimal Power, Performance, and Area (PPA) optimization, as they cannot adjust latency based on timing criticality, resulting in either improved input PPA at the cost of output PPA or vice versa.
Innovation Solution
A clock delay circuit that dynamically adjusts clock latency based on the polarity of the write enable signal, offering higher latency during write cycles and lower latency during read cycles, utilizing a combination of low and high skew portions to optimize memory operations, thereby improving write operation frequency and balancing data setup times across memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If constant clock latency is provided independent of read or write operation, then circuit design is simplified, but PPA optimization becomes sub-optimal as it cannot adjust latency based on timing criticality
Solution Approach 1:
The patent implements dynamic clock latency adjustment by selecting between different clock delay paths (first clock delay circuit for write operations, second clock delay circuit for read operations) based on the operation type. This dynamic reconfiguration allows the system to optimize PPA for each operation type independently, resolving the contradiction between circuit simplicity and PPA optimization.
2Reliability
If higher clock latency is provided to improve setup time on memory inputs, then input PPA is improved, but output PPA deteriorates due to negative impact on timing
Solution Approach 1:
The patent segments the clock distribution into two separate delay circuits: a first clock delay circuit for write operations that provides higher latency to improve input setup time, and a second clock delay circuit for read operations that provides lower latency to maintain output timing. This segmentation resolves the contradiction by allowing independent optimization of input and output PPA for different operation types.
3Productivity
If lower clock latency is provided to improve timing on memory output paths, then output PPA is improved, but input PPA deteriorates due to insufficient setup time margin
Solution Approach 1:
The patent dynamically switches between clock delay circuits based on operation type. During read operations, the second clock delay circuit provides lower latency to improve output timing, while during write operations, the first clock delay circuit provides higher latency to ensure adequate setup time. This dynamic adaptation resolves the contradiction between input and output PPA requirements.
4Device complexity
If constant clock latency is used, then clocking system design is simplified, but write operation frequency is limited and cannot be optimized
Solution Approach 1:
The patent segments the clocking system into operation-specific delay circuits, with the first clock delay circuit optimized for write operations. This segmentation enables write operation frequency optimization without significantly complicating the overall clocking system design, as each delay circuit is independently configured for its specific operation type.
Data Source
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AI summary
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.