Semiconductor Memory Clock Generator with Multi-Stage Phase Correction
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Solution Overview
Problem
High-speed semiconductor memory apparatuses face difficulties in correcting the phase of the clock, leading to frequent clock errors and reduced reliability due to shorter clock periods, which affects the operation of systems using these clock generators.
Innovation Solution
A clock generator design that includes a first divider, first and second delay units, a phase comparator, and a delay time setting unit, utilizing frequency-divided clocks for phase and duty cycle correction, allowing for stable and reliable clock generation by adjusting delay times based on phase comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of the semiconductor memory apparatus is increased, then the productivity is improved, but the clock period becomes shorter making phase correction difficult and reducing reliability
Solution Approach 1:
The patent divides the single delay correction stage into multiple delay stages (first delay element array and second delay element array). Each stage handles a portion of the total delay correction, allowing finer control over the clock phase adjustment. This segmentation enables effective phase correction even at high operation speeds where the overall clock period is short.
Solution Approach 2:
The patent implements dynamic delay adjustment through control signals that modify the delay time of delay elements based on detected phase differences. The delay element arrays can dynamically change their delay characteristics to compensate for phase errors, maintaining reliable clock generation across varying operating conditions and speeds.
2Productivity
If the operation speed of the semiconductor memory apparatus is increased, then the productivity is improved, but the phase correction becomes difficult leading to frequent clock errors
Solution Approach 1:
By dividing the delay correction into multiple stages with separate delay element arrays, the patent achieves finer granularity in phase adjustment. Each stage can be independently controlled to provide precise incremental delay changes, improving the overall precision of phase correction at high speeds.
Solution Approach 2:
The patent employs a feedback mechanism where the phase difference between clocks is detected and used to generate control signals that adjust the delay elements. This closed-loop feedback enables continuous refinement of the clock phase, achieving high precision correction even when the clock period is short due to high operation speeds.
3Device complexity
If a single delay element array is used for clock correction, then the device complexity is reduced, but the manufacturing precision of phase correction is insufficient
Solution Approach 1:
The patent uses multiple delay element arrays instead of a single array, dividing the correction function into discrete stages. While this increases structural complexity, each individual delay element can be manufactured with standard precision, and the cumulative effect of multiple stages achieves the required overall phase correction precision.
Data Source
AI summary
The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.