Memory Device Clock Divider Circuit Timing Skew
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Solution Overview
Problem
High-speed memory devices face challenges in securing timing margins, particularly when using the geardown mode, which can lead to timing skew due to the increased number of circuits required.
Innovation Solution
A memory device design that includes (n−1) numbered dividers to generate multiple divided clocks, a first delay to synchronize these clocks, a multiplexer (mux) to select one of the divided clocks, and a flip-flop to synchronize the selected clock with a signal, minimizing the number of circuits while preventing timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If geardown mode is used to lower clock frequency for high-speed operation, then operating speed is improved, but timing skew occurs due to increased number of circuits
Solution Approach 1:
The clock signal is divided into multiple divided clocks (second clock, third clock, fourth clock, etc.) with different frequencies using separate dividers. This segmentation allows selection of appropriate clock frequencies for different operating modes, enabling high-speed operation while managing timing requirements through frequency division rather than increasing circuit complexity.
Solution Approach 2:
The system dynamically selects different divided clocks based on operating mode requirements. A multiplexer (mux) chooses among multiple divided clocks (CLKD2, CLKD3, CLKD4, etc.) to synchronize with commands and data signals, allowing the system to adapt clock frequency dynamically without permanently increasing circuit complexity for all possible frequencies.
2Reliability
If multiple dividers are added to generate divided clocks for geardown mode, then timing margin is improved, but device complexity increases
Solution Approach 1:
Multiple divided clocks are generated from a single first clock signal using separate dividers, and a multiplexer selects among these divided clocks based on operating mode requirements. This universal approach allows the same clock generation structure to serve multiple frequency requirements, improving timing margin for different operating speeds without proportionally increasing overall device complexity.
Data Source
AI summary
A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.