Memory Clock Division Correction for Reliable Deserialization
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Solution Overview
Problem
In semiconductor memory systems, the interruption of clock signals during operation leads to synchronization issues between the memory device and the host, causing deserialization errors and requiring reinitialization of clock settings, which affects performance and power consumption.
Innovation Solution
A memory device with an internal clock generator, deserializer, and clock controller that corrects the clock dividing start time point by generating multiple internal clock signals with different phases, deserializing test data, and comparing it with reference data to synchronize operations, thereby maintaining clock signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory device enters interrupt mode and exits to resume operation, then the operation can be interrupted and resumed, but the clock signal synchronization between memory device and host is lost requiring reinitialization
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors the clock signal from the host and automatically adjusts its internal clock dividing start time point based on the received clock signal characteristics. This feedback loop ensures that after exiting interrupt mode, the memory device can autonomously resynchronize its clock signals without requiring host reinitialization, thus maintaining reliability while supporting interrupt mode operation
Solution Approach 2:
The patent performs preliminary clock synchronization actions by continuously tracking the host clock signal characteristics before interrupt mode is entered. The memory device pre-adjusts its internal clock dividing parameters based on the current clock signal state, so that when exiting interrupt mode, the synchronization is already partially established, reducing the reinitialization overhead and maintaining reliable operation
2Ease of operation
If the clock dividing start time point is not corrected after interrupt mode, then the device operation is simple, but deserialization errors occur due to clock signal desynchronization
Solution Approach 1:
The patent implements a self-service mechanism where the memory device automatically corrects its own clock dividing start time point using the clock signal received from the host. The device monitors its own deserialization accuracy and autonomously adjusts its internal clock parameters without external intervention, maintaining both operational simplicity and deserialization precision through self-correction
Solution Approach 2:
The patent introduces dynamic adjustment of the clock dividing start time point based on real-time clock signal characteristics. The memory device continuously adapts its internal clock parameters in response to changes in the host clock signal, ensuring accurate deserialization while maintaining simple operation through automated dynamic correction rather than fixed manual configuration
3Reliability
If multiple internal clock signals with different phases are generated, then clock signal synchronization can be improved, but the device complexity increases
Solution Approach 1:
The patent segments the clock signal generation into multiple phased internal clock signals, where each signal serves a specific function in the deserialization process. By dividing the clock generation into distinct phased components, the system achieves reliable synchronization while managing complexity through functional segmentation rather than a monolithic complex generator
Solution Approach 2:
The patent designs the internal clock generator to produce multiple phased signals that serve multiple functions simultaneously - the same clock distribution network provides synchronized clocks for different deserialization stages and error correction processes. This multi-functionality reduces overall device complexity by reusing the same clock infrastructure for multiple purposes rather than requiring separate dedicated clock generators for each function
Data Source
AI summary
A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.