Memory Clock Division Control for Setup and Hold Margin
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Solution Overview
Problem
Semiconductor memory apparatuses face reduced setup and hold margins for external signals as clock frequency increases, necessitating improved internal clock frequency control to maintain accurate operations.
Innovation Solution
A clock control circuit with a mode register set, delay unit, division command decoder, and division selection unit that adjusts the internal clock frequency based on mode register set and synchronization signals, allowing for the generation of a selection clock with a frequency equal to or lower than the external clock, thereby enhancing the setup and hold margins for command and address inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external clock frequency is increased for higher speed operations, then the productivity of the semiconductor memory apparatus is improved, but the setup and hold margins of external signals are reduced
Solution Approach 1:
The patent segments the clock signal processing by introducing a division command decoder that can divide the external clock frequency by 2 or 4 for command and address signals, while maintaining the original high frequency for data signals. This segmentation allows different signal types to operate at optimal frequencies, resolving the contradiction between high-speed operation and adequate setup/hold margins.
Solution Approach 2:
The patent implements dynamic clock frequency selection through a mode register set that can be configured to选择不同的时钟分频模式. The division command decoder dynamically adjusts the clock frequency based on the operation type and configured mode, enabling the system to adapt between high-speed data processing and reliable command/address processing.
2Speed
If the clock frequency is increased, then the data input speed is improved, but the setup and hold margins for commands and addresses are reduced
Solution Approach 1:
The patent applies segmentation by separating the clock frequency application: high frequency clocks are used for data input operations to maximize speed, while divided frequency clocks (1/2 or 1/4 of external clock) are used for command and address signals to ensure precise timing margins. This segmentation resolves the contradiction between speed and timing precision.
Solution Approach 2:
Different quality levels of clock signals are applied to different signal paths based on their requirements. Data paths receive high-frequency clocks for maximum speed, while command and address paths receive divided-frequency clocks with better timing characteristics. This local quality differentiation resolves the contradiction between overall speed and local timing precision.
Data Source
AI summary
An internal clock frequency control circuit of a semiconductor memory apparatus includes a mode register set configured to receive a mode register set control signal and output a mode register set signal; a delay unit configured to generate an enable signal when a predetermined cycle has elapsed after the mode register set signal was activated; a division command decoder configured to receive and decode a synchronization command to generate a division start signal when the enable signal is activated; and a division selection unit configured to receive an input clock having a first frequency and output a selection clock having a second frequency, wherein a value of the second frequency is substantially the same as the first frequency or lower than the first frequency depending on a level of the division start signal.