Memory Clock Drift Detection Using a Slow Timing Reference
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Solution Overview
Problem
Memory systems face timing drift issues due to temperature and voltage variations, causing phase misalignment between timing references in memory devices and controllers, which existing technologies fail to accurately detect and adjust for during data transport.
Innovation Solution
A memory system that uses a low-frequency slow clock signal to determine phase delays in a memory device, allowing for accurate drift detection and phase adjustment of high-frequency clock signals used for data transport, thereby maintaining synchronization despite temperature and voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency clock signals are used for data transport, then data transmission speed is improved, but timing drift due to temperature and voltage variations increases
Solution Approach 1:
A low-frequency slow clock signal is introduced as an intermediary carrier to transport timing reference information from the memory controller to the memory device. This slow clock signal is less susceptible to timing drift during transmission and serves as a stable reference for phase alignment, resolving the contradiction between high-speed data transport and timing reliability
Solution Approach 2:
The system performs preliminary phase alignment by embedding timing reference information in the slow clock signal before high-frequency data transmission begins. The memory device uses this advance timing information to pre-adjust its clock phases, ensuring synchronization is established before rapid data transfer starts, thus maintaining reliability at high speeds
2Measurement precision
If timing drift calibration is performed continuously, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
Instead of continuous calibration, the system performs timing drift calibration periodically using the slow clock signal. The low frequency of the slow clock naturally spaces out calibration events, reducing the frequency of high-power operations while maintaining adequate synchronization accuracy through periodic adjustments
Solution Approach 2:
The memory device autonomously extracts timing reference information from the received slow clock signal and performs self-calibration of its internal clock phases. This self-service approach eliminates the need for continuous external intervention and high-power calibration circuits, achieving accurate phase alignment with reduced power consumption
3Measurement precision
If complex calibration processes are used to detect timing drift, then detection accuracy is improved, but device complexity increases
Solution Approach 1:
The system uses a simplified copy approach where the slow clock signal carries a replicated version of the timing reference information from the memory controller. This copying method provides accurate timing drift detection without requiring complex calibration circuits, as the timing reference is directly embedded in the low-frequency signal that is inherently more stable and easier to process
Data Source
AI summary
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.