Memory Clock Delay Line with Dual-Edge Coarse Timing Shift
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Solution Overview
Problem
Conventional memory systems face significant area and power consumption due to long delay stages in delay chains, and existing digital delay lines with single edge-triggered flip-flops suffer from high latency and limited dynamic coarse delay shifting.
Innovation Solution
A digital delay line with a coarse delay line using dual-edge triggered clock counters for dynamic coarse delay shifting, combined with a fine delay line for finer delay steps, and a clock mux to bypass the input clock when unnecessary, reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional delay-cell based delay line design is used to achieve required delay range, then delay range is satisfied, but area and power usage increase significantly
Solution Approach 1:
The delay line is segmented into two independent parts: a coarse delay line using dual-edge triggered clock counters for large delay steps, and a fine delay line using delay cells for precise delay adjustment. This segmentation allows each part to be optimized independently, reducing the total number of delay cell stages needed while maintaining the required delay range.
Solution Approach 2:
The patent introduces dynamic delay adjustment capability through dual-edge triggered clock counters that can dynamically shift clock phases and delays based on control signals. This dynamic approach replaces static delay cell chains, enabling flexible delay adjustment without proportionally increasing area.
2Duration of action of moving object
If conventional delay-cell based delay line design is used to achieve required delay range, then delay range is satisfied, but power consumption increases significantly
Solution Approach 1:
The delay line is segmented into two independent parts: a coarse delay line using dual-edge triggered clock counters for large delay steps, and a fine delay line using delay cells for precise delay adjustment. This segmentation allows each part to be optimized independently, reducing the total number of delay cell stages needed while maintaining the required delay range.
Solution Approach 2:
The patent introduces dynamic delay adjustment capability through dual-edge triggered clock counters that can dynamically shift clock phases and delays based on control signals. This dynamic approach replaces static delay cell chains, enabling flexible delay adjustment without proportionally increasing area.
3Device complexity
If single edge-triggered flip-flops are used in digital delay line, then implementation is simple, but dynamic coarse delay shifting is not provided and latency is high
Solution Approach 1:
The patent introduces dynamic delay adjustment capability through dual-edge triggered clock counters that can dynamically shift clock phases and delays based on control signals. This dynamic approach replaces static delay cell chains, enabling flexible delay adjustment without proportionally increasing area.
Solution Approach 2:
The dual-edge triggered flip-flops utilize both rising and falling edges of the clock signal to increment the delay count, effectively doubling the utilization of the clock signal. This periodic action on both edges reduces the number of clock cycles needed for delay adjustment, thereby reducing latency.
4Duration of action of moving object
If delay stages are made long to reach required delay range, then delay range is satisfied, but area and power usage increase
Solution Approach 1:
The delay line is segmented into two independent parts: a coarse delay line using dual-edge triggered clock counters for large delay steps, and a fine delay line using delay cells for precise delay adjustment. This segmentation allows each part to be optimized independently, reducing the total number of delay cell stages needed while maintaining the required delay range.
Solution Approach 2:
The patent introduces dynamic delay adjustment capability through dual-edge triggered clock counters that can dynamically shift clock phases and delays based on control signals. This dynamic approach replaces static delay cell chains, enabling flexible delay adjustment without proportionally increasing area.
Data Source
AI summary
The invention relates to a digital delay line of a memory system is characterized by: a coarse delay line receiving a high-speed input clock; and a fine delay line transmitting an interface output clock to transceivers; wherein the coarse delay line is configured to perform clock division from a frequency of the high-speed input clock to a frequency of the interface output clock and to delay divided output clock; wherein the coarse delay line comprising a dual-edge triggered flip-flop to produce a shifted divided clock and a clock mux to bypass the high-speed input clock when delay shifting is not needed; wherein the fine delay line is configured to provide a finer delay step size. Further, a method of adjusting the timing of clocks within a memory system using a digital delay line of a memory system is also disclosed.