Memory Clock Duty Cycle Correction With Pump-Gated Power Saving
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Solution Overview
Problem
General duty cycle correction circuits in semiconductor memory apparatuses consume high current as they continuously operate to maintain equal high-level and low-level periods of a clock signal, leading to inefficient operational efficiency.
Innovation Solution
A duty cycle correction circuit that includes a duty ratio correcting unit, a duty ratio detecting unit, a pump enable signal generating unit, and a reference voltage generating unit, which corrects the duty ratio of a clock signal using reference voltages and enables the pump only when necessary to reduce current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a general duty cycle correction circuit continuously operates to maintain equal high-level and low-level periods of a clock signal, then the duty ratio correction is effective, but current consumption is large
Solution Approach 1:
The patent implements periodic action by using a pump enable signal to periodically activate the charge pump circuit only when duty ratio correction is needed. The circuit monitors the duty ratio and enables the pump in periodic intervals rather than continuous operation, thereby reducing current consumption while maintaining correction effectiveness when required.
Solution Approach 2:
The patent applies dynamics by making the pump enable signal controllable and adjustable based on actual duty ratio conditions. The circuit dynamically adjusts the operation state of the charge pump circuit according to the detected duty ratio deviations, transitioning between active and inactive states to optimize both correction performance and power consumption.
2Productivity
If a duty cycle correction circuit is implemented to correct clock signal duty ratio, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the duty ratio detection function and the correction control function into a unified circuit structure. The pump enable signal generating unit integrates the logic for detecting duty ratio deviations and generating control signals, combining multiple functions into a single modular block that reduces overall circuit complexity while maintaining operational efficiency.
Solution Approach 2:
The charge pump circuit serves multiple functions: it acts as both the duty ratio correction mechanism and the controlled element for power management. By making the pump enable signal controllable, the same circuit structure achieves both correction functionality and power consumption optimization, demonstrating multi-functionality that reduces the need for separate dedicated circuits.
Data Source
AI summary
A duty cycle correction circuit of a semiconductor memory apparatus includes a duty ratio correcting unit configured to correct a duty ratio of a clock signal according to levels of a first reference voltage and a second reference voltage, and to output the clock signal as a correction clock signal, a duty ratio detecting unit configured to count first and second counting signals in response to a duty ratio of the correction clock signal when a pump enable signal is enabled, a pump enable signal generating unit configured to generate the pump enable signal in response to the duty ratio of the correction clock signal, and a reference voltage generating unit configured to generate the first and second reference voltages in response to the first and second counting signals.