Memory Clock Correction Circuit for Multi-Phase Duty Training
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Solution Overview
Problem
Semiconductor memory devices face challenges in correcting phase skews and duty errors of multi-phase clock signals, leading to signal integrity issues due to internal circuit time delays and external clock synchronization.
Innovation Solution
A semiconductor memory device with a clock correction circuit that generates divided clock signals with 90-degree phase differences, adjusts skews, and performs sequential duty cycle training to search for optimal control code sets, enhancing signal integrity by correcting phase skews and duty errors during a duty training interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a circuit is used to compensate for time delay and correct duty error, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The clock correction circuit is divided into multiple independent functional blocks: a divided clock signal generation unit that creates quadrature-phase clock signals, a phase skew adjustment unit that corrects timing differences, and a duty cycle training unit that optimizes signal characteristics. This segmentation allows each block to perform its specific function with simpler circuitry while collectively achieving comprehensive clock signal correction.
Solution Approach 2:
The circuit performs preliminary duty cycle training and phase skew adjustment before normal memory operations begin. By pre-correcting clock signal parameters during initialization, the system eliminates the need for continuous complex correction circuits during operation, reducing overall device complexity while maintaining signal integrity.
2Manufacturing precision
If sequential duty cycle training is performed to search for optimal control code sets, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The duty cycle training is performed periodically during initialization rather than continuously. The system executes sequential training phases (first duty cycle training, second duty cycle training, third duty cycle training) that systematically search for optimal control codes, then maintains these settings during normal operation. This periodic approach achieves high precision without continuous time consumption.
Solution Approach 2:
The clock correction circuit autonomously performs duty cycle training and phase skew adjustment without requiring external intervention or continuous monitoring. The system self-calibrates by searching for optimal control code sets and automatically applies corrections, eliminating the need for manual adjustment or ongoing training processes that would consume additional time.
Data Source
AI summary
A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.