Memory Clock Duty Cycle Detection for High-Speed Write Paths
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Solution Overview
Problem
Current technologies face challenges in testing the duty cycle of high-speed clock signals, ensuring the accuracy of such tests, and generating equidistant parallel clock signals, which are crucial for improving memory performance.
Innovation Solution
A signal detection system is developed for a memory that performs a duty cycle test on output signals of test paths using a test circuit. This system includes a signal generator that produces a reference test signal with a preset duty cycle, allowing for the testing of different portions under test, such as signal converters and write clock paths, to ensure normal function and generate equidistant parallel clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed clock signal is used to improve data processing speed, then the speed of data processing is improved, but the difficulty of detecting and measuring the duty cycle increases
Solution Approach 1:
The patent segments the high-speed clock signal measurement into multiple manageable components: a test circuit that divides the clock signal into multiple test signals, integral circuits that process each test signal separately, and comparison circuits that compare the integrated results. This segmentation allows accurate duty cycle measurement of high-speed signals by breaking down the complex measurement task into simpler, parallel processing steps.
Solution Approach 2:
The patent introduces intermediary components to facilitate measurement: integral circuits serve as intermediaries between the high-speed clock signal and the measurement system, accumulating signal characteristics over time. The test circuit acts as an intermediary that transforms the difficult-to-measure high-speed clock signal into multiple slower test signals that are easier to process and compare.
2Productivity
If the transmission frequency of the clock signal is increased to improve the number of operations, then the productivity is improved, but the measurement precision of the duty cycle deteriorates
Solution Approach 1:
The patent applies preliminary action by using integral circuits to pre-process the test signals before comparison. The integral circuits accumulate the test signals over a predetermined time period, preparing the data in advance for accurate comparison. This preliminary integration ensures that even high-frequency signals are properly conditioned for measurement, maintaining precision regardless of clock speed.
Solution Approach 2:
The patent employs periodic action through the cyclic operation of the test circuit, which periodically generates test signals from the clock signal at different phases. The integral circuits periodically integrate these signals, and the comparison circuits periodically compare the results. This periodic measurement approach allows continuous monitoring of duty cycle at high speeds while maintaining measurement precision through repeated sampling.
3Measurement precision
If a test circuit is designed to measure duty cycle accurately, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated circuit blocks: the test circuit combines signal division, phase generation, and initial processing functions; the integral circuits combine signal accumulation and filtering functions; the comparison circuits combine differential measurement and decision logic. This merging reduces the overall system complexity by consolidating multiple discrete components into functional blocks while maintaining measurement precision.
Solution Approach 2:
The patent designs universal circuit blocks that can handle various clock signal frequencies and duty cycle ranges. The test circuit, integral circuits, and comparison circuits are designed as multi-functional units that can process different types of clock signals (write clocks, read clocks, inverted clocks) and measure duty cycles across a wide frequency range, reducing the need for multiple specialized circuits.
Data Source
AI summary
A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.