Memory Clock Correction Circuit for Skew and Duty Error Locking
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Solution Overview
Problem
Semiconductor memory devices face challenges in synchronizing clock signals due to internal circuit delays, leading to time delays and duty errors, which affect data transfer efficiency and accuracy.
Innovation Solution
A semiconductor memory device with a quadrature error correction circuit that generates corrected clock signals with a 90-degree phase difference by adjusting skew and duty errors, and performs relocking operations in response to a relock signal to maintain synchronization, enhancing performance and responsiveness to operating condition changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a circuit is used to compensate for time delay and duty error, then clock signal synchronization is improved, but device complexity increases
Solution Approach 1:
The quadrature error correction circuit dynamically adjusts skew and duty error parameters based on detected phase differences between clock signals. The circuit continuously monitors and corrects timing variations rather than using fixed compensation values, allowing adaptive synchronization without requiring overly complex static circuit designs.
Solution Approach 2:
The circuit employs feedback mechanisms where the phase relationship between first and second corrected clock signals is continuously monitored. Based on this feedback, the circuit adjusts skew and duty error parameters to maintain proper synchronization, enabling reliable operation without excessive circuit complexity through closed-loop control.
2Measurement precision
If quadrature error correction circuit performs continuous locking operation, then clock signal accuracy is improved, but loss of time occurs during relocking
Solution Approach 1:
The circuit maintains preliminary locking information and operational state even during periods when full locking operation is not required. This allows the circuit to quickly resume or continue synchronization without performing complete relocking procedures, reducing time loss while maintaining accuracy during active operation.
Solution Approach 2:
Instead of continuous locking operation, the circuit performs periodic or event-driven locking adjustments. The circuit monitors for specific conditions (such as initialization commands or relock signals) and performs locking operations only when necessary, reducing unnecessary time consumption while maintaining clock signal accuracy during normal operation.
3Manufacturing precision
If skew and duty error are adjusted to generate corrected clock signals, then data transfer accuracy is improved, but device complexity increases
Solution Approach 1:
The circuit achieves improved data transfer accuracy by adjusting key parameters (skew and duty error) of existing clock signals rather than introducing entirely new complex signal generation mechanisms. By modifying these critical parameters within the quadrature error correction circuit, high precision is achieved with relatively simple circuit architecture.
Data Source
AI summary
A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.