Memory System Clock Feedback Mechanism for Propagation Delay Cancellation
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Solution Overview
Problem
In memory systems, high-speed operation leads to increased propagation delays in clock and data transmission, making synchronized data transfer challenging, and encrypted communication synchronization becomes difficult with higher speeds, resulting in complex circuit designs and increased costs.
Innovation Solution
A memory system where the host device and memory device operate with separate clocks, with the memory device feeding back the first clock as the second clock, eliminating the need for a data strobe signal generation circuit and timing-adjustment circuit, and incorporating a correction mechanism to account for propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data transfer is performed in synchronization with a single common clock, then circuit design is simplified, but propagation delays increase with higher operation speeds making synchronized transfer difficult
Solution Approach 1:
The patent segments the single common clock into two separate clocks: a first clock for command transmission and a second clock for data reception. This segmentation allows each clock to be independently optimized for its specific function, enabling high-speed operation without the propagation delay issues that plague single-clock systems. The memory device generates the second clock based on the first clock, maintaining synchronization while allowing for speed optimization.
2Speed
If separate clocks are used for transmission and reception, then high-speed operation is enabled, but circuit complexity increases due to additional clock generation and timing adjustment circuits
Solution Approach 1:
The patent merges the clock generation function into the memory device itself, which already contains control circuits for managing data access. The control circuit within the memory device generates the second clock signal based on the first clock received from the host, combining clock generation with existing control functions rather than adding entirely separate clock generation hardware. This reduces overall system complexity while enabling separate-clock high-speed operation.
Solution Approach 2:
The memory device feeds back the first clock signal to its own control circuit, which then generates the second clock signal. This feedback mechanism ensures that the second clock remains synchronized with the first clock while allowing for independent timing optimization. The feedback loop enables precise timing adjustment without requiring complex external synchronization circuits.
3Device complexity
If encryption and decryption are performed in synchronization with a single clock, then implementation is simple, but synchronization becomes difficult at higher speeds
Solution Approach 1:
The patent applies segmentation to encryption and decryption operations by associating encryption with the first clock (command transmission) and decryption with the second clock (data reception). This segmentation allows each cryptographic operation to be synchronized with its respective clock, maintaining reliability at high speeds. The separate clocks ensure that encryption and decryption occur at appropriate times without interference, even at higher operation speeds where single-clock synchronization fails.
Data Source
AI summary
A control circuit of a memory device feeds a first clock received from a transmission control circuit of a host device back to a reception control circuit of the host device as a second clock. The reception control circuit controls data reception from the memory device in synchronization with the fed-back second clock.