Memory Clock Frequency Adjustment Circuit
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Solution Overview
Problem
In dynamic random access memory (DRAM) systems, frequent transitions between self-refresh modes to adjust frequency cause significant time delays and electromagnetic interference, especially when rapid frequency changes are needed.
Innovation Solution
A circuit comprising a frequency parameter generator, clock generator, and memory controller that adjusts the clock signal frequency gradually without entering the self-refresh mode, using an adjustment frequency determining circuit to detect access requirements and control the memory accordingly, thereby reducing the need for self-refresh mode transitions and minimizing electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the memory controller controls the DRAM to frequently enter and exit self-refresh mode for frequency adjustment, then the frequency can be changed, but significant time delays occur
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the clock frequency before the DRAM needs to enter self-refresh mode. The memory controller proactively changes the clock frequency in advance, so that when frequency adjustment is needed, the DRAM is already at the target frequency and doesn't need to enter self-refresh mode, thereby eliminating the time delay associated with mode transitions.
Solution Approach 2:
The patent introduces an intermediary mechanism - a frequency adjustment circuit that mediates between the memory controller and the DRAM clock source. This intermediary circuit allows smooth frequency transitions without requiring the DRAM to change operational modes, thus avoiding the time penalties of self-refresh mode transitions while still achieving frequency adjustment.
2Speed
If the memory controller controls the DRAM to frequently enter and exit self-refresh mode for frequency adjustment, then the frequency can be changed, but electromagnetic interference increases
Solution Approach 1:
The frequency adjustment circuit serves as an intermediary that smooths out abrupt frequency changes. By using this intermediate stage, the system can transition frequencies more gradually and controlledly, reducing the electromagnetic interference that would otherwise be generated by sudden mode transitions and frequency switches.
Solution Approach 2:
The patent applies parameter changes by continuously adjusting the clock frequency parameter through the frequency adjustment circuit rather than making discrete jumps between fixed frequencies via self-refresh mode transitions. This continuous parameter adjustment reduces electromagnetic interference by avoiding abrupt changes in operational state.
3Use of energy by stationary object
If the DRAM changes frequency only in self-refresh mode, then power saving can be achieved, but additional period for entering/exiting self-refresh mode is required
Solution Approach 1:
The system performs preliminary frequency adjustment through the frequency adjustment circuit before power-saving mode transitions are needed. This allows the DRAM to maintain optimal frequency for performance while still entering self-refresh mode only when truly needed for power saving, rather than using self-refresh mode as the primary frequency adjustment mechanism.
Solution Approach 2:
The patent segments the frequency adjustment function from the power management function. Frequency adjustment is handled by the dedicated frequency adjustment circuit, while power saving is handled by selective entry into self-refresh mode. This separation allows each function to operate independently and efficiently without compromising the other.
4Speed
If the memory controller frequently controls the memory to enter/exit self-refresh mode, then frequency can be adjusted, but system stability deteriorates due to long periods of time delay
Solution Approach 1:
The frequency adjustment circuit acts as a stable intermediary that handles all frequency changes without requiring the DRAM to leave its current operational mode. This eliminates the instability and long delays associated with frequent self-refresh mode transitions, maintaining system stability while providing frequency adjustability.
Solution Approach 2:
The patent ensures continuous useful action by maintaining the DRAM in a stable operational mode while the frequency adjustment circuit continuously provides frequency control. This avoids the intermittent disruptions caused by repeated mode transitions, thereby maintaining system stability and continuous operation.
Data Source
AI summary
A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal.