Semiconductor Memory Clock Selection for Stable High-Frequency Output
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Solution Overview
Problem
Conventional semiconductor memory apparatuses face operational stability issues when performing high-speed data output operations due to the limitations of either delay locked loop (DLL) or phase locked loop (PLL) circuits, which are not adaptable to a wide frequency band and require negative delay circuits, leading to unreliable data output.
Innovation Solution
A semiconductor memory apparatus that incorporates a DLL circuit for generating a DLL clock signal, a PLL circuit activated based on frequency discrimination, and a clock selection unit to selectively output either the DLL or PLL clock signal, ensuring stable operation across high-frequency environments without a negative delay circuit in the PLL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL circuit is used for clock signal generation, then stability to jitter component and adaptability to PVT in low-frequency operation are improved, but suitability for high-frequency operation deteriorates
Solution Approach 1:
The patent implements a dynamic clock signal generation system that automatically switches between DLL and PLL circuits based on operating frequency requirements. The frequency discrimination unit detects the input clock frequency and activates the appropriate circuit (DLL for low-frequency, PLL for high-frequency), allowing the system to adapt its clock generation mechanism dynamically to maintain both jitter stability and high-frequency capability.
2Speed
If a PLL circuit with negative delay circuit is used for high-frequency operation, then suitability for high-frequency operation is improved, but operational stability deteriorates
Solution Approach 1:
The patent extracts the negative delay function from the PLL circuit and implements it separately in the DLL circuit. The PLL circuit is configured without a negative delay circuit, which eliminates the stability deterioration issue while maintaining high-frequency operation capability. The DLL circuit handles the negative delay requirement independently when operating at low frequencies.
3Device complexity
If only DLL or only PLL circuit is used, then device complexity is reduced, but adaptability to wide frequency band deteriorates
Solution Approach 1:
The patent creates a universal clock signal generation system where both DLL and PLL circuits are integrated into a single apparatus. The frequency discrimination unit determines which circuit to activate based on the input frequency, enabling the system to handle both low-frequency and high-frequency operations with appropriate circuit selection, thus achieving wide frequency band adaptability without requiring separate dedicated systems.
4Speed
If PLL circuit is activated continuously to ensure high-frequency capability, then high-frequency operation capability is maintained, but current consumption increases
Solution Approach 1:
The patent implements periodic activation of the PLL circuit based on frequency discrimination. The frequency discrimination unit continuously monitors the input clock frequency and activates the PLL circuit only when high-frequency operation is detected. During low-frequency operation, the PLL circuit remains inactive, significantly reducing current consumption while maintaining the capability to switch to high-frequency mode when needed.
Data Source
AI summary
A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.