Memory Clock Derivation from Gated Data Clock Pins
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Solution Overview
Problem
Existing DRAM chips face challenges in achieving higher data bandwidth while maintaining a compact circuit size and minimizing power consumption, particularly with the increase in the number of data pins.
Innovation Solution
Deriving a system clock (CK) from a gated data clock (WCK) within the memory device, reducing the need for separate transmission and allowing the reuse of I/O pins for data transmission, and employing revised command bus encoding to support more complex multi-cycle commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data pins is increased to achieve higher data bandwidth, then data transmission capacity is improved, but circuit size and power consumption increase
Solution Approach 1:
The patent combines the system clock signal (CK) and data clock signal (WCK) transmission by using the same I/O pin for both purposes. The memory controller transmits CK and WCK on overlapping time periods through the same pin, eliminating the need for separate dedicated clock pins and reducing overall pin count while maintaining high data bandwidth capability
Solution Approach 2:
The I/O pins are designed to serve multiple functions: they can transmit system clock signals, data clock signals, and data signals themselves. This multi-functionality allows the memory interface to achieve high bandwidth with fewer pins, thereby reducing power consumption compared to dedicated single-function pin designs
2Productivity
If the number of data pins is increased to achieve higher data bandwidth, then data transmission capacity is improved, but circuit size increases
Solution Approach 1:
The patent merges the transmission channels for system clock and data clock signals by allowing them to share the same I/O pin through time-division multiplexing. This consolidation reduces the total number of pins required in the memory interface, directly reducing circuit size while preserving high data bandwidth capability
Solution Approach 2:
The patent introduces time as an additional dimension for signal transmission by using time-division multiplexing. Instead of allocating separate spatial resources (dedicated pins) for clock signals, the system utilizes temporal separation to allow multiple signals to share the same physical pin, effectively reducing the spatial footprint of the circuit
3Reliability
If separate system clock and data clock signals are transmitted, then clock signal reliability is improved, but the number of I/O pins increases
Solution Approach 1:
The patent combines the transmission of system clock (CK) and data clock (WCK) signals by allowing them to share the same I/O pin during overlapping time periods. This merging approach maintains the reliability of both clock signals while reducing the total pin count from four dedicated pins (CK+, CK-, WCK+, WCK-) to a smaller number of shared pins
4Reliability
If more I/O pins are used for clock signal transmission, then clock signal quality is improved, but power consumption increases
Solution Approach 1:
The patent merges clock signal transmission functions into shared I/O pins, reducing the total number of active signal paths. Fewer pins require fewer drivers and receivers, which directly reduces the power consumption associated with clock signal transmission while maintaining signal quality through proper time-division multiplexing
Data Source
AI summary
A memory system comprises a memory controller coupled to a memory device. The memory controller is configured to generate and transmit a data clock signal to the memory device. The memory controller does not transmit a system clock signal to the memory device. The memory device is configured to receive the data clock signal and internally generate a system clock signal based on the data clock signal according to a ratio. The data clock signal from the memory controller is a gated data clock signal that is transmitted to the memory device based on a demand from command or data traffic between the memory controller and the memory device.