Semiconductor Memory Clock Generation for High-Speed Testing
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Solution Overview
Problem
Less expensive test devices cannot generate high frequency clock signals necessary for testing semiconductor memory devices operating at frequencies over 1 GHz, limiting their ability to adequately test these devices.
Innovation Solution
A semiconductor memory device that generates first and second clock signals with the same phase and frequency as an external clock signal during normal operations, and a higher frequency second clock signal during test operations, allowing for data conversion between serial and parallel formats to accommodate different data rates, enabling effective testing with lower frequency test instruments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If expensive test devices are used to generate high frequency clock signals for testing, then testing capability is improved, but testing cost increases
Solution Approach 1:
The memory device generates its own high-frequency clock signals internally using a clock signal generating means that receives external clock signals and generates first and second clock signals at the same or higher frequencies. This self-service approach eliminates the need for expensive external test devices to provide high-frequency clock signals, allowing standard test equipment to adequately test high-frequency memory devices
Solution Approach 2:
A clock signal generating means acts as an intermediary between the external test device and the memory device. This intermediary receives low-frequency clock signals from inexpensive test devices and generates the required high-frequency clock signals internally, enabling standard test equipment to test high-frequency memory devices effectively
2Adaptability or versatility
If data is converted between serial and parallel formats to accommodate different data rates, then compatibility with test devices is improved, but device complexity increases
Solution Approach 1:
The data write means and data read means dynamically adjust their operation mode based on the test mode. During normal operations, the device operates in parallel mode, while during test operations, it dynamically switches to serial-parallel conversion mode. This dynamic adaptation allows the device to accommodate different test requirements without permanently increasing complexity
Solution Approach 2:
The data write means and data read means are designed with multi-functionality to handle both normal parallel data operations and test serial data operations. By integrating both functions into the same hardware blocks, the device achieves versatility in accommodating different test devices without requiring separate dedicated circuits, thereby limiting the increase in overall device complexity
3Measurement precision
If the memory device generates higher frequency clock signals during test operations, then testing accuracy is improved, but power consumption increases
Solution Approach 1:
The clock signal generating means operates periodically based on the operation mode. During normal operations, it generates clock signals at the same frequency as external clock signals. During test operations, it periodically generates higher frequency clock signals only when needed for testing, rather than continuously. This periodic adjustment of frequency based on operational requirements improves testing accuracy while limiting unnecessary power consumption during normal operations
Data Source
AI summary
A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array.