Memory Clock Characteristic Optimization via Genetic Algorithm
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Solution Overview
Problem
High-speed integrated circuit devices face challenges in reliable data transfer due to reduced data eye size as data transfer rates increase, with previous approaches failing to effectively improve data transfer reliability at higher rates.
Innovation Solution
The method involves determining and optimizing clock characteristics for memory devices using a genetic algorithm to generate new clock characteristics, increasing the data eye size by selecting and mutating clock settings that improve fitness, thereby enhancing data transfer reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased, then productivity is improved, but data eye size decreases making reliable data transfer difficult
Solution Approach 1:
The patent applies parameter changes by optimizing clock characteristics (such as clock frequency, phase, and duty cycle) of memory devices to resolve the contradiction between data transfer rate and reliability. By dynamically adjusting these temporal parameters, the system achieves larger data eye sizes at higher data rates, enabling both improved productivity and maintained reliability simultaneously
2Reliability
If clock characteristics are optimized using genetic algorithm, then data eye size increases, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling memory devices to automatically optimize their own clock characteristics through embedded genetic algorithms. The system performs self-testing and self-optimization without requiring external intervention, thereby increasing data eye size and reliability while keeping the complexity management contained within the device itself
Data Source
AI summary
A method includes varying a number of clock characteristics of each a plurality of memory devices of a memory concurrently, determining a fitness of the memory for each variation of the number of clock characteristics, selecting a particular variation of the number of clock characteristics based on the determined fitness of the memory for the particular variation, changing a setting in each of the plurality of memory devices corresponding to the particular variation to generate an additional variation of the number of clock characteristics, and determining a fitness of the memory for the additional variation.