Memory Clock Buffering With Logic-Gated Hold Time Reduction
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Solution Overview
Problem
Conventional memory clock buffering introduces significant delay due to resistor-capacitor (RC) loading, increasing hold times for data signals in subsequent arrays of columns, and existing solutions like programmable delay circuits consume substantial die space and power.
Innovation Solution
A logic gate is used to process two versions of the memory clock signal, where one version is buffered and drives the first array of columns, and the other, unloading version propagates quickly to trigger the logic gate for the second array, minimizing delay and hold times by avoiding RC loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the memory clock signal is buffered in a clock repeater to restore signal strength for driving multiple arrays, then the clock signal strength is restored, but the hold time for data signals is increased due to introduced delay
Solution Approach 1:
The patent segments the clock signal paths into two separate versions: a first version that drives the first array of columns through the clock repeater, and a second version that is used to trigger the logic gate for the second array. This segmentation allows each path to be optimized independently - the first path gets the necessary buffering for strength while the second path maintains speed for low hold time requirements.
Solution Approach 2:
The patent introduces a logic gate as an intermediary element that processes the two versions of the clock signal. The logic gate takes the buffered first version and the unbuffered second version as inputs, and generates the clock signal for the second array. This intermediary allows the system to benefit from both the strength restoration of buffering and the speed of unbuffered signaling.
2Loss of time
If programmable delay circuits are used to reduce hold time requirements, then the hold time is reduced, but die space and power consumption are substantially increased
Solution Approach 1:
The patent replaces complex, space-consuming programmable delay circuits with a simple logic gate that processes clock signals. The logic gate is a much simpler, smaller component that achieves the same functional goal of managing timing relationships without requiring the substantial die space and power consumption of programmable delay circuits.
3Strength
If the memory clock signal is buffered to drive multiple arrays, then signal strength is restored, but power consumption is increased due to RC loading
Solution Approach 1:
The patent segments the clock signal distribution into two versions, allowing only the necessary portions to be buffered. The second version of the clock signal that triggers the logic gate is not subjected to RC loading from driving columns, thereby reducing overall power consumption while still maintaining adequate signal strength where needed.
Data Source
AI summary
A memory is provided with a logic gate that processes a first version and a second version of a memory clock signal to assert a clock signal for the clocking of latches in a second array of columns for the memory. The first version clocks the latches in a first array of columns for the memory. But the second version does not clock any latches in the first array of columns.