Memory Data Clock Training for ISI-Resilient Logic Level Detection
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Solution Overview
Problem
High-speed data transfer between processors and memory devices is hindered by distortion in data clock signals due to inter-symbol interference (ISI), making it difficult for memory devices to accurately detect logic level transitions.
Innovation Solution
A memory device and method that includes a divide circuit to generate internal data clock signals, a detect circuit to provide feedback data based on these signals, and an input/output circuit to output this feedback to an external device, with a host device determining an optimal preceding voltage level by adjusting duty cycles using DCA codes to minimize distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data clock frequency is increased to achieve high-speed data transfer, then the data transfer speed is improved, but the accuracy of logic level detection deteriorates due to ISI distortion
Solution Approach 1:
The patent applies preliminary action by adjusting the duty cycle of the data clock signal before transmission to compensate for anticipated ISI distortion. The host device performs duty cycle adjustment (DCA) based on training feedback to pre-correct the clock signal characteristics, ensuring that even at high frequencies, the memory device can accurately detect logic levels despite channel distortion.
Solution Approach 2:
The patent implements feedback through a training mechanism where the memory device monitors the received data clock signal quality and provides feedback information to the host device. The host device uses this feedback to iteratively adjust the duty cycle parameters, creating a closed-loop system that optimizes signal integrity for accurate detection at high transfer speeds.
2Measurement precision
If the duty cycle of the data clock signal is adjusted to compensate for ISI distortion, then the logic level detection accuracy is improved, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent applies universality by implementing the duty cycle adjustment functionality within existing data transfer infrastructure. The host device's existing clock generation and control circuits are extended to perform DCA, and the training feedback mechanism integrates with standard memory initialization sequences. This avoids adding entirely separate complex subsystems while achieving improved detection accuracy.
3Reliability
If a training feedback mechanism is implemented to determine optimal duty cycle parameters, then the data clock signal quality is improved, but the initialization time is increased
Solution Approach 1:
The patent applies partial action by implementing a staged training approach where the full duty cycle optimization is performed only when needed. During normal operation, the system uses previously optimized parameters, and training is triggered only when signal quality degradation is detected or during system initialization. This reduces the time penalty compared to continuous training while maintaining reliable signal quality.
Data Source
AI summary
A memory device includes a divide circuit configured to generate an internal data clock signal based on a data clock signal, wherein the data clock signal has a first voltage level for a first time period and toggles during a second time period consecutive to the first time period, a detect circuit configured to generate a feedback data corresponding to the first voltage level based on the internal data clock signal, and an input/output circuit configured to output the feedback data to an external device.