Memory Clock Level-Shifting Buffer Extended Range
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level shifters in integrated circuits have a limited operating range, which restricts the voltage difference between the peripheral and bitcell array domains, leading to increased access time and power consumption, and difficulty in maintaining stable voltage supplies for memory operations.
Innovation Solution
A level shifter circuit with an input clock buffer that receives parallel clock signals from both the peripheral and bitcell array domains, allowing for extended voltage range operation without latency penalties, by generating an output clock signal based on a predetermined threshold voltage, and incorporating a dual rail design with inverters to introduce delay and manage transistor operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional level shifter is used to shift voltage levels between peripheral and bitcell array domains, then voltage level shifting is achieved, but the operating range is limited and access time increases
Solution Approach 1:
The level shifter circuit is segmented into multiple independent clock buffers (first clock buffer, second clock buffer, third clock buffer) that can operate independently. Each buffer handles specific voltage level transitions, allowing the circuit to accommodate a wider range of voltage differences between domains without increasing access time, as each segment is optimized for its specific function
Solution Approach 2:
The circuit dynamically selects which clock buffer to use based on the actual voltage levels in the peripheral and bitcell array domains. The level shifter can adapt its operation mode (using first, second, or third clock buffer) depending on whether the voltage difference is small or large, enabling extended operating range while maintaining optimal access time characteristics
2Adaptability or versatility
If a conventional level shifter is used to shift voltage levels, then voltage level shifting is achieved, but power consumption increases
Solution Approach 1:
Each clock buffer is designed with specific local characteristics optimized for particular voltage level transitions. The first clock buffer is optimized for certain voltage ranges while the second and third buffers are optimized for other ranges, allowing the system to use the most energy-efficient buffer for the current operating conditions, thereby reducing overall power consumption while supporting extended voltage ranges
3Power
If the voltage difference between peripheral and bitcell array domains is large, then higher power level shifting is achieved, but stability of voltage supply deteriorates
Solution Approach 1:
The level shifter circuit acts as an intermediary between the peripheral domain and bitcell array domain, providing a stable transition path for clock signals across large voltage differences. The multiple clock buffers with different threshold voltages create intermediate stages that stabilize the voltage transition, preventing direct large-swing transitions that would cause instability in either domain
Data Source
AI summary
A level shifter circuit includes a level shifter configured to receive a first clock signal associated with a first power level and generate a second clock signal associated with a second power level, wherein the second power level is greater than the first power level. The level shifter circuit further includes an input clock buffer having a first input, wherein the first input comprises the second clock signal from the level shifter, and a second input coupled in parallel to the first input, wherein the second input includes the first clock signal.