Memory Clock Mirroring via Switching Units
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Solution Overview
Problem
Conventional memory systems with parallel architecture face signal integrity issues due to the load applied on data input/output lines when operating in high bandwidth modes, such as X32, as the signal lines connecting multiple memory chips form a stub structure, leading to decreased performance.
Innovation Solution
A memory device and system configuration that includes switching units to selectively connect electrode pads and clock signal lines based on control signals, allowing operation in both X16 and X32 modes by isolating or connecting pads accordingly, thereby reducing signal line load and stub effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are connected in parallel architecture to increase memory capacity and bandwidth, then memory capacity and data input/output bandwidth are improved, but signal integrity deteriorates due to load on data input/output lines and stub structure formation
Solution Approach 1:
The patent segments the clock signal distribution by providing separate clock signal lines for first and second memory chips instead of sharing a common clock line. This segmentation prevents the stub structure that would form if both chips shared the same clock line, thereby maintaining signal integrity while supporting parallel operation of multiple chips to achieve increased memory capacity and bandwidth
Solution Approach 2:
The patent transitions from a single-plane clock distribution approach to a multi-dimensional approach by routing clock signals through different paths: one clock line connects to the first memory chip while another clock line connects to the second memory chip, potentially through different layers or routes on the circuit board. This dimensional separation eliminates the stub effect while maintaining the parallel architecture benefits
2Productivity
If 32-bit data input/output lines are connected to both memory chips, then X32 mode bandwidth is achieved, but signal integrity decreases due to increased load on each data line
Solution Approach 1:
The patent segments the data bus connectivity by configuring the first memory chip to connect to a first set of data lines while the second memory chip connects to a second set of data lines. This segmentation allows each chip to drive its own dedicated data lines, maintaining signal integrity while collectively providing X32 bandwidth through the combined capacity of both chips operating in parallel
Data Source
AI summary
A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.