Memory Clock Mode Circuit for Serial Flash Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing parallel configuration of Flash memory systems faces performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, leading to increased power consumption and limitations in the number of memory devices that can be connected, which restricts high-speed operation and increases costs.
Innovation Solution
A serially connected memory system with a ring topology configuration, where memory devices are connected in series, allowing for the use of either parallel or serial clock signals, and a configurable clock mode circuit that sets the operating mode based on a reference voltage, enabling efficient clock signal distribution and data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are connected in parallel to increase storage capacity, then the available storage capacity is improved, but signal integrity is degraded due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent divides the parallel memory device connections into multiple serial chains, where each chain connects a subset of memory devices in series. This segmentation reduces the number of parallel signals required, thereby improving signal integrity while maintaining the ability to access multiple devices. The memory controller can selectively activate different chains based on the storage capacity requirements.
2Quantity of substance
If the number of parallel memory devices is increased to meet ultra-high capacity demand, then storage capacity is improved, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
By segmenting the memory system into multiple serial chains, the patent reduces the total number of signal tracks that need to be charged and discharged simultaneously. This segmentation directly reduces power consumption while still providing access to the same total storage capacity through selective chain activation.
3Quantity of substance
If more memory devices are connected in parallel, then storage capacity is improved, but device complexity increases due to the need for more chip enable signals and clock routing
Solution Approach 1:
The patent segments the memory devices into multiple chains, each requiring fewer control signals. This reduces the total number of chip enable signals and simplifies clock routing compared to a fully parallel configuration, while still supporting the same number of memory devices.
Solution Approach 2:
The patent transitions from a two-dimensional parallel connection architecture to a multi-dimensional serial-chain architecture. This dimensional change allows the system to scale to more memory devices without proportionally increasing the complexity of control signals and clock routing.
4Speed
If the system operates at higher clock frequencies to improve performance, then speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic clocking within each serial chain, allowing the system to achieve high-speed operation when needed while enabling lower-power modes when full performance is not required. The memory controller can selectively enable or disable chains based on workload requirements.
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.