Memory Clock Mode Configuration for Serial Flash Signal Integrity
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Solution Overview
Problem
Existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, which degrade performance and increase power consumption, especially with increasing system clock frequencies, and are limited by the number of memory devices that can be connected in parallel.
Innovation Solution
A memory system architecture that connects memory devices in a serial ring topology, allowing for configurable operation modes between parallel and serial clock signals, using a clock mode configuration circuit to adapt to different signaling formats and minimize signal distribution issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent segments the memory system into multiple independent channels, each operating separately with its own clock signal. This segmentation isolates signal paths to prevent crosstalk and simultaneous switching noise between channels, while still achieving high storage capacity through parallel channel operation.
Solution Approach 2:
The patent transitions from a single-plane parallel architecture to a multi-channel three-dimensional architecture. By adding the channel dimension, the system can connect more memory devices without increasing signal interference on any single signal path, as each channel operates independently with dedicated signaling.
2Productivity
If system clock frequency is increased to improve operation speed, then productivity increases, but power consumption increases and signal integrity issues worsen
Solution Approach 1:
The patent employs double data rate (DDR) operation where data is transferred on both rising and falling edges of the clock signal. This periodic action on both edges effectively doubles the data transfer rate for the same clock frequency, improving productivity without increasing power consumption or clock speed.
Solution Approach 2:
The patent changes the signaling parameter from single-edge sampling to double-edge sampling. By utilizing both rising and falling edges of the clock signal for data capture, the system achieves higher effective data rates without increasing the fundamental clock frequency, thereby avoiding the associated power consumption and signal integrity penalties.
3Quantity of substance
If more memory devices are connected in parallel, then storage capacity increases, but the number of signal paths and complexity increase
Solution Approach 1:
The patent segments the memory system into multiple independent channels, each with its own dedicated signal paths and clock signals. This segmentation organizes the complexity into manageable units, where each channel can be independently controlled and managed, reducing the overall system complexity compared to a monolithic parallel connection.
Solution Approach 2:
The patent introduces a channel dimension to organize memory devices, transforming the signal distribution problem from a two-dimensional plane to a three-dimensional structure. This allows systematic management of signal paths through channel assignment, where each channel has dedicated resources, reducing cross-interference and simplifying signal distribution control.
4Productivity
If parallel clock signals are used to operate multiple memory devices, then productivity increases, but signal skew and simultaneous switching noise increase
Solution Approach 1:
The patent segments the clock distribution into separate dedicated clock signals for each channel. By providing individual clock paths rather than sharing common clock lines, the system eliminates signal skew between channels while maintaining high data transfer rates through parallel channel operation.
Data Source
AI summary
A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.