Memory Clock Mode Switching for High-Density Flash Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise (SSN), as well as power consumption concerns, when multiple memory devices are connected in parallel.
Innovation Solution
A semiconductor device with a configurable input circuit that can operate in two modes: one for receiving coincident edges of the clock and input data, and another for receiving non-coincident edges, allowing for efficient clock edge positioning within a data valid window. This device also includes a mode setter, a clock switch, and a configurable data input/output buffer to adapt to different clock modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the storage capacity is improved, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The invention divides the parallel-connected memory devices into groups, with each group having its own dedicated clock input. This segmentation reduces the number of devices sharing a common clock line, thereby reducing crosstalk and signal skew between devices while still achieving high storage capacity through the grouped parallel architecture.
Solution Approach 2:
The invention introduces an intermediary clock distribution structure that provides dedicated clock paths to groups of memory devices. This intermediary architecture acts as a buffer between the clock source and individual devices, reducing simultaneous switching noise and signal integrity issues while maintaining the ability to connect multiple devices for increased capacity.
2Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the storage capacity is improved, but power consumption increases due to simultaneous switching
Solution Approach 1:
The invention segments memory devices into groups with dedicated clock inputs, allowing independent control of clock signaling to each group. This enables selective activation of clocking to only those groups currently being accessed, reducing simultaneous switching across all devices and thereby lowering overall power consumption while maintaining high storage capacity.
3Quantity of substance
If additional channels are added to connect more memory devices, then the storage capacity is improved, but device complexity increases
Solution Approach 1:
The invention creates a universal clock distribution architecture where a single clock input can serve multiple memory devices through a grouping mechanism. This multi-functional approach allows the same clock infrastructure to support varying numbers of devices without requiring additional dedicated channels for each device, thereby increasing capacity while controlling system complexity.
Data Source
AI summary
A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.