Memory System Clock Modulation for Data Reliability Verification
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Solution Overview
Problem
Current memory devices lack an efficient method to verify the reliability of read data, leading to potential errors and inefficiencies in data transfer between memory devices and controllers.
Innovation Solution
A memory system that employs clock modulation and demodulation techniques to generate and verify the reliability of read data by using a modulation clock with multiple sections, allowing for detection and re-reading of abnormal data sections, thereby enhancing data integrity and transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred using a data clock between memory device and controller, then data transfer efficiency is improved, but there is no mechanism to verify reliability of transferred data
Solution Approach 1:
The patent combines data transfer and reliability verification into a single integrated process by embedding verification information within the data clock signal itself. The clock signal carries both timing information and verification data, eliminating the need for separate verification channels while maintaining transfer efficiency.
Solution Approach 2:
The data clock signal is designed to serve multiple functions simultaneously: it provides timing synchronization for data transfer and carries verification information for reliability checking. This multi-functional approach allows the same signal to improve both productivity and reliability without requiring additional dedicated signals.
2Reliability
If clock modulation is used to embed verification information, then data reliability verification is improved, but system complexity increases
Solution Approach 1:
The patent modifies parameters of the existing clock signal (such as frequency, phase, or duty cycle) to encode verification information. By changing clock parameters rather than adding separate verification signals, the system achieves reliability verification while minimizing increases in overall system complexity.
Solution Approach 2:
The clock signal acts as an intermediary that carries both timing and verification information. Instead of requiring direct separate channels for timing and verification, the clock mediates both functions, simplifying the system architecture compared to having entirely separate verification pathways.
3Reliability
If entire data set is re-read upon detecting errors, then data reliability is improved, but time consumption increases
Solution Approach 1:
The verification process is segmented by allowing selective re-reading of only the specific data sections that contain errors, rather than re-reading the entire data set. The clock modulation enables identification of which specific sections need verification, dividing the re-reading operation into targeted segments to minimize time loss.
Solution Approach 2:
Instead of performing a complete re-read of all data when errors are detected, the system performs a partial re-read of only the affected sections. This partial action approach maintains data reliability by re-reading necessary portions while avoiding the time penalty of re-reading unnecessary data sections.
Data Source
AI summary
A memory system including: a memory device looping back a first clock to generate a second clock and outputting read data that are read from a memory cell region of the memory device in synchronization with the second clock; and a memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock. The read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme.