Memory Clock Termination Circuit for Single-Ended Noise Isolation

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Solution Overview

Problem

Existing memory technologies face limitations in data transfer rates and power consumption due to the constraints of single-ended (SE) mode signaling, where noise interference and reduced slew rates hinder performance, while differential mode signaling increases power usage.

Innovation Solution

A high-impedance node termination circuit is implemented to selectively operate in either SE or differential mode, terminating unused clock lines to prevent noise and optimize power usage by grounding them or providing a stable reference voltage, thereby improving signal recovery and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If differential mode signaling is used to increase data transfer rates, then speed is improved, but power consumption increases

Engineering Contradiction:

Improvedata transfer rateVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The termination circuit is configured to dynamically switch between differential mode and single-ended mode based on operational requirements. The circuit can adapt its termination configuration to match the signaling mode being used, optimizing both performance and power consumption for each mode

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If single-ended mode signaling is used to conserve power, then power consumption is reduced, but noise interference increases

Engineering Contradiction:

Improvepower consumptionVSAvoidnoise interference

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The termination circuit acts as an intermediary element that interfaces between the single-ended signal line and ground/reference. By providing a controlled termination path, it mediates the signal environment to reduce noise interference while maintaining the power-saving benefits of single-ended mode

Inventive Principle:

Principle #24Intermediary (Mediator)

3Use of energy by moving object

If single-ended mode signaling is used to reduce power consumption, then power is conserved, but slew rate decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidslew rate

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The termination circuit modifies the electrical parameters of the single-ended signal line by providing a controlled termination impedance. This parameter change optimizes the signal characteristics to improve slew rate while maintaining the lower power consumption advantage of single-ended mode

Inventive Principle:

Principle #35Parameter changes

4Device complexity

If unused clock lines are left floating in single-ended mode, then device complexity is reduced, but noise interference increases

Engineering Contradiction:

Improvecircuit configurationVSAvoidnoise interference

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The termination circuit extracts and isolates the unused clock line from the active signaling path by providing a dedicated termination path to ground or reference. This separates the unused line's noise potential from the active signal, reducing interference while maintaining simple circuit configuration

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11804261B2Termination for single-ended mode

Publication Date: 2023.10.31 MICRON TECHNOLOGY INC

AI summary

This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.