Duty Cycle Monitor Offset Setting for Memory Clock Correction
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations, as existing duty cycle adjuster circuits require accurate settings to effectively improve duty cycle, but may not suffice unless set accurately.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a mode register, allowing for precise adjustment of internal clock duty cycles through programmable DCA codes, which can compensate for systemic duty cycle errors by monitoring and adjusting the timing of internal data clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjuster circuits require accurate settings to be effective
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors its own clock duty cycle performance and automatically adjusts the duty cycle adjuster circuit settings based on measured deviations. The memory device sends duty cycle adjustment requests to the controller, which then modifies the adjuster settings to compensate for observed distortion, creating a closed-loop system that eliminates the need for manual accurate presetting.
Solution Approach 2:
The memory device performs self-diagnosis and self-adjustment of its clock duty cycle by monitoring its own internal clock signals and automatically requesting setting modifications from the controller. This self-service approach allows the system to maintain optimal duty cycle accuracy without requiring external intervention or complex preconfiguration.
2Reliability
If duty cycle adjuster circuits are implemented, then internal clock timing is improved, but system complexity increases due to additional control mechanisms
Solution Approach 1:
The duty cycle adjuster circuit is integrated into the existing memory device architecture and serves multiple functions: it adjusts duty cycle based on automatic feedback requests, operates under controller management, and maintains compatibility with standard memory operations. The controller also maintains its existing command management role while gaining the additional function of managing duty cycle adjustments, reducing overall system complexity through multi-functionality.
Solution Approach 2:
The patent merges the duty cycle adjustment functionality with the existing memory control interface by utilizing the same command and data transfer mechanisms between controller and memory device. The mode register settings that control duty cycle adjustment are integrated into the existing memory device configuration space, allowing the adjustment mechanism to be controlled through standard memory management protocols without adding separate control infrastructure.
3Measurement precision
If automatic duty cycle adjustment is implemented through mode register settings, then duty cycle monitoring precision is improved, but the number of control parameters increases
Solution Approach 1:
The duty cycle adjustment control is segmented into discrete, manageable components: a duty cycle adjuster enable bit that activates the feature, a duty cycle adjuster setting field that specifies the adjustment magnitude, and a duty cycle adjuster polarity bit that determines adjustment direction. This segmentation allows precise control through a small number of well-defined parameters rather than requiring complex continuous adjustment mechanisms.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.