Duty Cycle Monitor Offset Setting for Memory Clock Correction

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Solution Overview

Problem

Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations, as existing duty cycle adjuster circuits require accurate settings to effectively improve duty cycle, but may not suffice unless set precisely.

Innovation Solution

The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a semiconductor device's mode register, allowing for precise adjustment of internal clock duty cycles through programmable DCA codes and DCM sequences to compensate for systemic duty cycle errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjuster circuits require accurate settings to be effective

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidadjuster circuit setting complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the memory device measures its own duty cycle distortion and automatically adjusts the duty cycle adjuster circuits based on these measurements. The controller sends test commands and measures the returned clocks to determine duty cycle distortion, then programs the adjuster circuits accordingly, eliminating the need for manual accurate setting while maintaining reliability

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The memory device performs self-diagnosis and self-adjustment of duty cycle distortion. By incorporating duty cycle measurement capabilities and automatic adjustment logic within the memory device, the system enables the device to service itself without requiring external intervention or complex manual configuration, thereby reducing setting complexity while maintaining duty cycle accuracy

Inventive Principle:

Principle #25Self-service

2Productivity

If duty cycle measurement and adjustment features are added to the memory device, then operational performance is improved, but device complexity increases

Engineering Contradiction:

Improvememory operation reliabilityVSAvoidcircuit feature complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent integrates duty cycle measurement and adjustment functionality into existing memory device components, allowing these components to serve multiple functions. The same circuits used for normal memory operations are leveraged for duty cycle measurement and adjustment, thereby improving operational reliability without proportionally increasing device complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The duty cycle measurement and adjustment features are merged with the existing control and timing circuits within the memory device. By combining these functions into integrated circuits rather than adding separate discrete components, the patent improves productivity while minimizing the increase in device complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250022496A1Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

Publication Date: 2025.01.16 LODESTAR LICENSING GROUP LLC

AI summary

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.