Memory Clock Circuit Path Switching for Rate-Adaptive Synchronization
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Solution Overview
Problem
Current Dynamic Random Access Memory (DRAM) technologies face challenges in achieving optimal synchronization and power efficiency due to varying data transmission rates, which affect the performance and power consumption of clock signals in memory systems.
Innovation Solution
A clock circuit with a data strobe clock circuit and a system clock circuit, featuring multiple signal transmission paths that adapt to different data transmission rates, using Current Mode Logic (CML) frequency dividers for high-speed and Complementary Metal Oxide Semiconductor (CMOS) frequency dividers for low-speed transmissions to ensure strong anti-interference capability and low power consumption respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock transmission path is used for both high-speed and low-speed data transmission, then device complexity is reduced, but synchronization performance deteriorates at different data rates
Solution Approach 1:
The clock transmission system is segmented into multiple independent transmission paths: a first transmission path for high-speed data and a second transmission path for low-speed data. Each path is optimized for its specific speed range, allowing the system to maintain synchronization performance across different operating conditions without excessive complexity.
Solution Approach 2:
The system dynamically selects which transmission path to use based on the actual data transmission rate. When the data rate exceeds the threshold, the first transmission path is activated; otherwise, the second path is used. This dynamic adaptation ensures optimal synchronization performance for the current operating condition.
2Reliability
If CML frequency dividers are used for high-speed transmission, then synchronization performance is improved, but power consumption increases
Solution Approach 1:
Different transmission paths with different power characteristics are assigned to different speed ranges. The first transmission path (optimized for high-speed with higher power consumption) is only activated when high-speed transmission is required. The second transmission path (optimized for low-speed with lower power consumption) is used for normal operation, achieving local optimization of power efficiency.
Solution Approach 2:
The system changes the operational parameters by switching between different transmission paths based on data rate thresholds. This parameter change allows the system to adapt power consumption levels to actual performance requirements, avoiding unnecessary power consumption during low-speed operation.
3Reliability
If multiple transmission paths are used for different data rates, then synchronization performance is improved, but device complexity increases
Solution Approach 1:
The clock transmission system is designed with multi-functionality to handle both high-speed and low-speed data transmission through different paths. Each transmission path is universal in its ability to carry clock signals but specialized in its optimization for specific speed ranges, allowing the system to maintain reliability across varying conditions.
4Use of energy by moving object
If CMOS frequency dividers are used for low-speed transmission, then power consumption is reduced, but anti-interference capability deteriorates
Solution Approach 1:
The system applies local quality optimization by matching the transmission path characteristics to the specific operating conditions. The second transmission path (with lower power consumption but reduced anti-interference capability) is only used when data rates are low and interference susceptibility is less critical. The first transmission path (with better anti-interference capability) is used for high-speed transmission where signal integrity is more demanding.
Data Source
AI summary
A clock circuit and a memory are provided. The clock circuit includes a data strobe clock circuit and a system clock circuit. The data strobe clock circuit is configured to receive and transmit a data strobe clock signal, the data strobe clock signal is used for controlling at least one of receiving or sending of a data signal. The system clock circuit is configured to receive and transmit a system clock signal, the system clock signal is used for controlling receiving of a command signal. The system clock circuit includes at least two first signal transmission paths, and is configured to transmit the system clock signal via different first signal transmission paths in the at least two first signal transmission paths based on at least one of: different receiving rates, or different sending rates of the data signal.