Memory Clock Synchronization Using WCK Pattern Alignment
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Solution Overview
Problem
The frequency change of the data clock signal WCK in LPDDR DRAM devices causes increased circuit complexity and reduced signal quality due to the need for synchronization with the clock signal CK, which is not efficiently addressed by existing technologies.
Innovation Solution
A memory device and controller method that synchronizes the data clock signal WCK with the clock signal CK using a synchronization pattern without altering the frequency of WCK, achieved through a data clock splitter and synchronization pattern implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data clock signal WCK frequency is changed to synchronize with the clock signal CK, then the synchronization between data clock and clock signal is improved, but the circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by performing synchronization operation before normal data transmission. The memory device receives synchronization patterns during a preliminary synchronization period, adjusts the phase of the data clock signal WCK to match the clock signal CK, and then enters normal operation mode. This pre-synchronization approach eliminates the need for continuous frequency adjustment circuits during data transmission, thereby reducing circuit complexity while maintaining reliable synchronization.
2Reliability
If the data clock signal WCK frequency is changed to synchronize with the clock signal CK, then the synchronization between data clock and clock signal is improved, but the signal quality deteriorates
Solution Approach 1:
The patent implements periodic action by using periodic synchronization patterns transmitted at regular intervals during the synchronization process. These periodic patterns allow the memory device to make incremental phase adjustments to the data clock signal WCK, maintaining signal stability throughout the synchronization process. The periodic nature of the synchronization patterns prevents signal quality deterioration by providing consistent reference points for phase alignment without requiring continuous frequency changes.
3Reliability
If the data clock signal WCK frequency is reduced to half for synchronization, then the synchronization with clock signal CK is achieved, but the operating speed decreases
Solution Approach 1:
The patent applies dynamics by making the data clock signal WCK frequency adjustable and dynamic rather than fixed. During the synchronization period, the data clock frequency is temporarily reduced to half to enable reliable phase alignment with the clock signal CK. Once synchronization is achieved, the system dynamically transitions to normal operating frequency. This dynamic frequency adjustment approach maintains both synchronization reliability and high operating speed during normal data transmission.
Data Source
AI summary
A method of operating a memory device includes receiving, from a memory controller, an operation command that is synchronized with a clock signal, receiving a data clock signal having a full-rate frequency and a synchronization pattern provided by at least one of a plurality of data signals. The clock signal and the data clock signal are then synchronized using a synchronization operation based on the synchronization pattern. The data clock signal may be received after a first delay time passes from a time point at which the operation command is received. The first delay time is a delay time necessary to prepare the synchronization operation.