Semiconductor Memory Clock Pattern Generating Unit EMI Reduction
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Solution Overview
Problem
Volatile semiconductor memory devices, such as DRAMs, face challenges in minimizing Electromagnetic Interference (EMI) due to similar waveform patterns output through error detection code pins during clocking modes, which can interfere with data transmission and reception reliability.
Innovation Solution
A semiconductor memory device with a clock pattern generating unit that outputs distinct pseudo random binary pattern signals through multiple detection clock output pins, grouping them into different waveform patterns controlled by an output selection signal, thereby reducing EMI by generating the same or different phases and waveforms depending on the signal state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the same clock pattern is output through multiple detection clock output pins, then the circuit design is simplified and ease of operation is improved, but electromagnetic interference increases and reliability deteriorates
Solution Approach 1:
The patent applies local quality by making different detection clock output pins output different clock patterns (first clock pattern vs. second clock pattern) instead of the same pattern. This creates local differentiation in the signal characteristics at different pins, reducing electromagnetic interference while maintaining the overall system functionality. The controller can selectively receive different patterns from different pins based on local signal quality requirements.
2Reliability
If different clock patterns are output through multiple detection clock output pins, then electromagnetic interference is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamics by making the clock pattern output configurable and switchable. The detection clock output pins can dynamically change their output patterns based on control signals from the controller. This allows the system to adapt between different operational modes (same pattern vs. different patterns) without permanent hardware modifications, balancing reliability improvement with manageable complexity through software/control signal management.
3Reliability
If distinct pseudo random binary pattern signals are generated through multiple pins, then electromagnetic interference is minimized and data transmission reliability is enhanced, but the complexity of signal generation and control increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple detection clock output pins to output different clock patterns (first and second patterns) before actual data transmission begins. The controller receives these pre-established patterns and uses them for clock data recovery and error detection. This preliminary setup ensures that reliable different patterns are already available when needed, without requiring complex real-time generation during data transmission.
Data Source
AI summary
A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.