Memory Clock Control Circuit for Four-Phase Timing Alignment
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Solution Overview
Problem
The phase difference between multi-phase clock signals in memories, such as DDR5 DRAM, is affected by duty cycle variations of external clock signals, leading to decreased signal quality and prolonged duty cycle adjustment training times.
Innovation Solution
A clock control circuit with a delay adjustment circuit and determination circuit that records and compares phase sequences of clock signals at self-refresh exit timings, adjusting delays based on a determination result signal to ensure consistent phase differences, thereby improving accuracy and reducing training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle adjustment training is performed to correct phase differences caused by external clock signal variations, then signal quality is improved, but training time is prolonged
Solution Approach 1:
The determination circuit records the phase sequence of clock signals at self-refresh exit timing in advance, before duty cycle adjustment training begins. This preliminary recording allows the delay adjustment circuit to pre-determine which delay adjustment mode to apply, eliminating the need for time-consuming phase sequence detection during training and reducing overall training time while maintaining signal quality
Solution Approach 2:
The determination circuit continuously monitors and records phase sequences at self-refresh exit timing, providing feedback information about clock signal phase relationships. This feedback enables the delay adjustment circuit to adaptively select appropriate delay adjustment strategies, optimizing both signal quality and training efficiency
2Measurement precision
If delay adjustment is performed during duty cycle adjustment training mode, then phase difference accuracy is improved, but the complexity of clock control increases
Solution Approach 1:
The clock control circuit is segmented into distinct functional modules: a determination circuit for recording phase sequences, a delay adjustment circuit for applying delay corrections, and a mode register for storing control parameters. This segmentation allows each module to perform its specific function independently, simplifying the overall control logic while improving phase difference accuracy
Solution Approach 2:
A mode register serves as an intermediary between the determination circuit and the delay adjustment circuit. The mode register stores control codes that encode phase sequence information and delay adjustment parameters, acting as a buffer that simplifies the interface between different circuit components and reduces control complexity
Data Source
Figure 1
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AI summary
Embodiments of the present disclosure provide a clock control circuit, a memory, and a clock control method, where the clock control circuit includes: a delay adjustment circuit, configured to receive a first phase clock signal, a second phase clock signal, a third phase clock signal, a fourth phase clock signal, and a determination result signal, and adjust delays of the second phase clock signal, the third phase clock signal, and the fourth phase clock signal or adjust delays of the first phase clock signal, the second phase clock signal, and the fourth phase clock signal according to the determination result signal in a duty cycle adjustment training mode; and a determination circuit, configured to record a phase sequence of the first phase clock signal and the third phase clock signal at self-refresh exit timing, then compare the phase sequence of the first phase clock signal and the third phase clock signal at the self-refresh exit timing with a phase sequence of the first phase clock signal and the third phase clock signal at previous self-refresh exit timing, and output the determination result signal according to whether the two phase sequences are consistent or not. The disclosed embodiments are advantageous for at least improving the phase differences between the four-phase clock signals.