Memory Clock Phase Correction Using Quadrature Edge Detection
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Solution Overview
Problem
High-speed semiconductor memory devices face reliability issues due to phase errors in clock signals, which decrease operation accuracy and margin, especially as integration increases and duty cycles decrease, making it challenging to synchronize data transfer at precise phases of the system clock.
Innovation Solution
A phase correction circuit using quadrature phase clocks to detect and correct phases of internal clocks to 0 degrees, 90 degrees, 180 degrees, and 270 degrees, employing edge detectors, comparators, control signal generators, and phase correctors to generate quadrature phase signals, ensuring accurate synchronization and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of the semiconductor memory device is increased, then the data transfer rate is improved, but the phase error in clock signals increases, decreasing operation reliability
Solution Approach 1:
The phase correction circuit performs preliminary correction of clock signal phases before the clock signals are used for data transfer operations. By detecting phase errors in advance and applying correction delays, the system ensures accurate phase alignment is established before high-speed operations begin, preventing reliability issues from phase mismatches.
Solution Approach 2:
The phase correction circuit continuously monitors the phases of clock signals and dynamically adjusts them based on detected phase errors. The circuit compares actual clock phases against reference phases and applies real-time corrections, creating a closed-loop feedback system that maintains phase accuracy even as operating conditions change.
2Productivity
If the integration level of the semiconductor memory device is increased, then the device functionality is improved, but the phase detection accuracy decreases due to line width reduction
Solution Approach 1:
The phase correction circuit is divided into multiple independent functional modules: phase detection units for each clock pair, comparison circuits, and separate correction circuits. This segmentation allows each module to be optimized independently and reduces the cumulative impact of manufacturing variations on overall phase detection accuracy.
Solution Approach 2:
The circuit adjusts operational parameters such as delay amounts and reference phases dynamically based on detected phase errors. By changing these parameters in real-time rather than relying on fixed design values, the circuit compensates for manufacturing tolerances and maintains accurate phase detection despite fine line width constraints.
3Productivity
If the duty cycle of the clock signal is decreased, then the data transfer efficiency is improved, but the error ratio in phase detection increases
Solution Approach 1:
The phase correction circuit dynamically adapts to varying duty cycles by continuously monitoring clock signal characteristics and adjusting correction parameters accordingly. Rather than being optimized for a fixed duty cycle, the circuit remains flexible and responsive, maintaining accurate phase detection across different duty cycle conditions that arise during high-efficiency data transfer operations.
4Device complexity
If the phase correction circuit uses traditional correction methods, then the circuit complexity is reduced, but the operation margin is insufficient leading to failures
Solution Approach 1:
The phase correction circuit introduces intermediary correction stages between the clock signal source and the data transfer logic. These intermediary circuits provide buffer zones that absorb phase variations and ensure adequate operation margins, preventing direct propagation of phase errors to critical data paths.
Data Source
AI summary
A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.