Memory Clock Phase Distortion Mitigation via Trim Parameter Selection
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Solution Overview
Problem
Existing memory systems face challenges in mitigating distortion in multi-phase clock signals, which affects signal quality and system performance, especially when the response of memory systems falls outside the average range indicated by pre-determined trim parameters.
Innovation Solution
A low-speed tester measures the change in phase of clock signals in response to configuration changes in the memory system, storing the difference, which is then used by a high-speed tester to select trim parameters for the multi-phase clock, thereby mitigating distortion and improving signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pre-determined trim parameters are used to mitigate distortion in multi-phase clock signals, then the process is simple and fast, but the accuracy is insufficient when memory system response falls outside the average range
Solution Approach 1:
The patent applies preliminary action by measuring and storing the response characteristics of clock signals at different phases during a low-speed testing phase before the actual high-speed operation. These pre-measured response values are then used to accurately determine trim parameters during high-speed testing, avoiding the need for complex real-time measurements while maintaining high accuracy.
Solution Approach 2:
The patent introduces an intermediary approach by using response values measured at a low-speed testing phase as intermediate data. These intermediate measurements serve as a foundation for calculating accurate trim parameters during the high-speed phase, bridging the gap between simple pre-determined values and complex real-time measurements.
2Productivity
If high-speed testing is performed directly without low-speed preliminary measurements, then the testing speed is fast, but the ability to accurately determine trim parameters for non-average cases is reduced
Solution Approach 1:
The patent performs preliminary measurements at low-speed to capture the actual response characteristics of the memory system before conducting high-speed testing. This preliminary action ensures that the system's specific response behavior is recorded, enabling accurate trim parameter determination even for non-average cases while maintaining overall testing efficiency.
Solution Approach 2:
The patent implements a dynamic testing approach that adapts to the specific memory system being tested. By measuring response values during low-speed phase and using them to guide high-speed testing, the system dynamically adjusts the trim parameter determination process to match the actual characteristics of each memory system, rather than using static pre-determined values.
Data Source
AI summary
Methods, systems, and devices for techniques for coupled host and memory dies are described. As part of a low-speed testing phase of a memory system, a low-speed tester may measure the change in phase of a set of clock signals in response to a change in a configuration of the memory system. For example, the low-speed tester may communicate with a mimic circuit of the memory system to determine a first frequency of a first clock signal of the multi-phase clock associated with a first configuration of the memory system and determine a second frequency of the first clock signal associated with a second configuration of the memory system. The low-speed tester may store an indication of the difference between the first frequency and the second frequency, and a high-speed tester may use the difference as part of selecting a set of trim parameters for the multi-phase clock signal.